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公开(公告)号：US20220337251A1
公开(公告)日：2022-10-20
申请号：US17856643
申请日：2022-07-01
IPC分类号： H03K19/17796 , G06F30/347 , H03K19/17736 , H01L25/065
摘要： Systems and methods are provided for system circuitry disaggregation into an integrated circuit system with multiple chiplets having disaggregated components. A system may include a first programmable logic fabric die that includes programmable logic circuitry and a number of supporting chiplets that include disaggregated field programmable gate array (FPGA) circuitry. The chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement.
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公开(公告)号：US20220013488A1
公开(公告)日：2022-01-13
申请号：US17484922
申请日：2021-09-24
申请人： Mahesh K. Kumashikar , Dheeraj Subbareddy , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
发明人： Mahesh K. Kumashikar , Dheeraj Subbareddy , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
IPC分类号： H01L23/00 , H01L25/065 , H01L23/48 , H01L25/00
摘要： An integrated circuit device includes multiple microbumps and a top programmable fabric die including a first programmable fabric and a first microbump interface coupled to the multiple microbumps. The integrated circuit device also includes a base programmable fabric die having a second programmable fabric and a second microbump interface coupled to the first microbump interface via a coupling to the multiple microbumps. The top programmable fabric die and the base programmable fabric die have a same design. Moreover, the top programmable fabric die and the base programmable fabric die are arranged in a three-dimensional die arrangement with the top programmable fabric die flipped above the base programmable fabric die.
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23.发明申请FREQUENCY CONTROL SYSTEM WITH DUAL-INPUT BIAS GENERATOR TO SEPARATELY RECEIVE MANAGEMENT AND OPERATIONAL CONTROLS 有权具有双输入偏置发电机的频率控制系统，以分别接收管理和运行控制公开(公告)号：US20140340129A1
公开(公告)日：2014-11-20
申请号：US13977424
申请日：2012-04-13
CPC分类号： H03L7/16 , H03L7/0802 , H03L7/0893 , H03L7/0895 , H03L7/093 , H03L7/099 , H03L7/1072 , H03L2207/06
摘要： Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode.
摘要翻译： 控制相对于参考频率的输出频率的方法和系统。 频率控制系统包括双输入偏置发生器，用于分别接收管理和操作控制。 偏置发生器包括：第一偏置发生器电路，用于在第一操作模式期间基于管理控制和偏置反馈参考之间的差异产生偏置控制;第二偏置发生器电路，用于基于第一偏置发生器电路之间的差产生偏置控制; 在第二操作模式期间的操作控制和偏置反馈参考，以及偏置反馈参考电路，以基于偏置控制产生偏置反馈参考。 第一模式可以包括表征和/或启动模式。 第二模式可以包括诸如反馈控制模式的操作模式。
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公开(公告)号：US07471102B2
公开(公告)日：2008-12-30
申请号：US11710359
申请日：2007-02-23
申请人： Atul Maheshwari , Greg Taylor
发明人： Atul Maheshwari , Greg Taylor
CPC分类号： G01R31/2884 , G01R31/2621
摘要： In one embodiment, the present invention includes an oscillator to generate a first frequency and a second frequency. The oscillator includes a plurality of stage cells, each stage cell including a first transistor of a first polarity and a second transistor of a second polarity, each coupled between a first voltage node and a first intermediate node and an inverter coupled to the first intermediate node. In operation, a difference between the first frequency and the second frequency is proportional to a threshold voltage of the second transistor. Other embodiments are described and claimed.
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公开(公告)号：US07332937B2
公开(公告)日：2008-02-19
申请号：US11321328
申请日：2005-12-28
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , G01R31/3008 , G01R31/31721 , H03K19/00361 , H03K19/00384
摘要： Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.
摘要翻译： 这里公开了用于向动态逻辑电路提供自适应保持器功能的解决方案。 在一些实施例中，可编程保持器电路耦合到寄存器文件电路。 包括泄漏指示器电路，用于在寄存器文件的至少一部分中建模泄漏。 控制电路耦合到泄漏指示器电路和可编程保持器电路，以根据建模的泄漏来控制保持器强度。 要求保护或以其他方式公开其他实施例。
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公开(公告)号：US07279939B2
公开(公告)日：2007-10-09
申请号：US11113614
申请日：2005-04-25
IPC分类号： G01R19/00
CPC分类号： H03F3/45 , G11C7/062 , H03K3/356121 , H03K3/356165
摘要： Returning to FIG. 2, sense circuit 201 represents the circuit that must sense the signaling on an interconnect. NMOS device 202 is always on so that there is a continuous path to ground whenever PMOS driver 204 is on. Since leakage power is an order of magnitude less than static and dynamic power it can be omitted for clarity, although it should be noted that dynamic power increases with respect to line length since the interconnect capacitance increases as line length increases. Static power is due to flow of static current across the two resistances shown in FIG. 2, interconnect resistance 206 and the resistance of transistors 102 and 104 from FIG. 1, represented by the resistance of equivalent NMOS transistor 208 of FIG. 2.
摘要翻译： 返回到图 如图2所示，感测电路201表示必须感测互连上的信令的电路。 NMOS器件202总是导通，使得每当PMOS驱动器204导通时，存在连续的接地路径。 由于泄漏功率比静态和动态功率小一个数量级，因此为了清楚起见，可以省略泄漏功率，尽管应该注意到，随着线路长度增加，互连电容增加，动态功率相对于线路长度增加。 静态功率是由于图2所示的两个电阻之间的静电流的流动引起的。 2，互连电阻206和来自图2的晶体管102和104的电阻。 由图1的等效NMOS晶体管208的电阻表示。 2。
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公开(公告)号：US20050237088A1
公开(公告)日：2005-10-27
申请号：US11113614
申请日：2005-04-25
CPC分类号： H03F3/45 , G11C7/062 , H03K3/356121 , H03K3/356165
摘要： Circuit for differential current sensing with reduced static power. Embodiments of the present invention provide a reduced static power differential current sense amplifier (DCSA) that can use a self-timed shutoff system to disable the sense amplifier after sensing is done and enable the sense amplifier before the start of sensing. The current sense amplifier can include at least two cross-coupled inverters. A decoupling mechanism connected to the cross-coupled inverters can be provided. The decoupling mechanism accepts a sense enable (SE) signal that selectively enables and disables the current sense amplifier. A discharge mechanism can also be connected to the cross-coupled inverters to remove excess charge. A selectively enabled low impedance path from the cross-coupled inverters to ground can also be provided.
摘要翻译： 具有降低静态功耗的差分电流检测电路。 本发明的实施例提供了一种减小的静态功率差分电流检测放大器（DCSA），其可以使用自定时关断系统在感测完成之后禁用读出放大器，并且在感测开始之前使读出放大器能够使能。 电流检测放大器可以包括至少两个交叉耦合的反相器。 可以提供连接到交叉耦合逆变器的去耦机构。 去耦机构接受有选择地启用和禁用电流检测放大器的感测使能（SE）信号。 放电机构也可以连接到交叉耦合的逆变器以去除多余的电荷。 还可以提供从交叉耦合的逆变器到地的选择性地启用的低阻抗路径。
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公开(公告)号：US20220336415A1
公开(公告)日：2022-10-20
申请号：US17856193
申请日：2022-07-01
IPC分类号： H01L25/065 , H01L23/48 , H01L23/00
摘要： Systems and methods are provided for a modular die-to-die interconnect for integrated circuits in a three-dimensional arrangement. An integrated circuit system may include a first chiplet that includes a grid-based interconnect field and a second chiplet that includes a complementary grid-based interconnect field. A number of interconnects of the complementary grid-based interconnect field of the second chiplet are connected to a corresponding number of interconnects of the grid-based interconnect field of the first chiplet.
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公开(公告)号：US20220116041A1
公开(公告)日：2022-04-14
申请号：US17559287
申请日：2021-12-22
申请人： Mahesh K. Kumashikar , Ankireddy Nalamalpu , MD Altaf Hossain , Dheeraj Subbareddy , Atul Maheshwari , Yuet Li , Mahesh A. Iyer
发明人： Mahesh K. Kumashikar , Ankireddy Nalamalpu , MD Altaf Hossain , Dheeraj Subbareddy , Atul Maheshwari , Yuet Li , Mahesh A. Iyer
IPC分类号： H03K19/177
摘要： Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.
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30.发明授权Frequency control system with dual-input bias generator to separately receive management and operational controls 有权频率控制系统采用双输入偏置发生器，分别接收管理和操作控制公开(公告)号：US09450592B2
公开(公告)日：2016-09-20
申请号：US13977424
申请日：2012-04-13
CPC分类号： H03L7/16 , H03L7/0802 , H03L7/0893 , H03L7/0895 , H03L7/093 , H03L7/099 , H03L7/1072 , H03L2207/06
摘要： Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode.
摘要翻译： 控制相对于参考频率的输出频率的方法和系统。 频率控制系统包括双输入偏置发生器，用于分别接收管理和操作控制。 偏置发生器包括：第一偏置发生器电路，用于在第一操作模式期间基于管理控制和偏置反馈参考之间的差异产生偏置控制;第二偏置发生器电路，用于基于第一偏置发生器电路之间的差产生偏置控制; 在第二操作模式期间的操作控制和偏置反馈参考，以及偏置反馈参考电路，以基于偏置控制产生偏置反馈参考。 第一模式可以包括表征和/或启动模式。 第二模式可以包括诸如反馈控制模式的操作模式。
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