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公开(公告)号：US07471102B2
公开(公告)日：2008-12-30
申请号：US11710359
申请日：2007-02-23
申请人： Atul Maheshwari , Greg Taylor
发明人： Atul Maheshwari , Greg Taylor
CPC分类号： G01R31/2884 , G01R31/2621
摘要： In one embodiment, the present invention includes an oscillator to generate a first frequency and a second frequency. The oscillator includes a plurality of stage cells, each stage cell including a first transistor of a first polarity and a second transistor of a second polarity, each coupled between a first voltage node and a first intermediate node and an inverter coupled to the first intermediate node. In operation, a difference between the first frequency and the second frequency is proportional to a threshold voltage of the second transistor. Other embodiments are described and claimed.
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公开(公告)号：US20080204156A1
公开(公告)日：2008-08-28
申请号：US11710359
申请日：2007-02-23
申请人： Atul Maheshwari , Greg Taylor
发明人： Atul Maheshwari , Greg Taylor
IPC分类号： H03B5/00
CPC分类号： G01R31/2884 , G01R31/2621
摘要： In one embodiment, the present invention includes an oscillator to generate a first frequency and a second frequency. The oscillator includes a plurality of stage cells, each stage cell including a first transistor of a first polarity and a second transistor of a second polarity, each coupled between a first voltage node and a first intermediate node and an inverter coupled to the first intermediate node. In operation, a difference between the first frequency and the second frequency is proportional to a threshold voltage of the second transistor. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括产生第一频率和第二频率的振荡器。 振荡器包括多个级单元，每个级单元包括第一极性的第一晶体管和第二极性的第二晶体管，每一个耦合在第一电压节点和第一中间节点之间，以及反相器耦合到第一中间节点 。 在操作中，第一频率和第二频率之间的差异与第二晶体管的阈值电压成比例。 描述和要求保护其他实施例。
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公开(公告)号：US20230028475A1
公开(公告)日：2023-01-26
申请号：US17957204
申请日：2022-09-30
IPC分类号： H01L23/538 , H01L23/498 , H03K19/17736 , H03K19/1776 , H01L25/065
摘要： A system includes a first die having a first side with first die-to-die circuitry and first input output circuitry. The system also includes a second die comprising a second side with second die-to-die circuitry and second input output circuitry. The first and second sides are adjacent to each other in the electronic package device. The system also includes a semiconductor interconnect including multiple connections to interconnect the first and second die-to-die circuitries. The semiconductor interconnect also includes multiple through-silicon-vias to transmit data to or from the first and second input output circuitries through the semiconductor bridge.
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公开(公告)号：US20220337250A1
公开(公告)日：2022-10-20
申请号：US17856479
申请日：2022-07-01
IPC分类号： H03K19/17736 , H03K19/1776 , H03K19/17728
摘要： This disclosure is directed to methods of disaggregating columnar IO operations from a programmable logic fabric using 3-D packaging technology. More specifically, methods of 3-D programmable fabric arrangements that include one or more IO chiplets stacked in a 3-D orientation on a programmable logic fabric main die that includes one or more D2D drivers to enable communication between the one or more IO chiplets and the programmable logic fabric main die. The IO chiplets may be coupled to the programmable fabric main die through connection to the one or more D2D drivers arranged on the programmable fabric main die.
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公开(公告)号：US20220229941A1
公开(公告)日：2022-07-21
申请号：US17711779
申请日：2022-04-01
摘要： Systems or methods of the present disclosure may provide a semiconductor device including a die of a multi-die package including encryption circuitry to receive data and to encrypt the data to generate encrypted data; and a connection interface to transmit the encrypted data over a die-to-die interconnect to a second die.
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公开(公告)号：US08314725B2
公开(公告)日：2012-11-20
申请号：US12883125
申请日：2010-09-15
IPC分类号： H03M1/10
摘要： In one embodiment, an analog-to-digital conversion in an integrated circuit is evaluated by an on-die testing circuit. For example, the on-die test circuit 370 can characterize one or both of the linearity and monotonicity of the digital-to-analog conversion. The value of a conversion output for a digital input code may be compared to the value of a prior conversion output of a prior step to provide digital difference values for each step of a sweep of digital input codes. Digital difference values may be compared to one or more predetermined limits to provide one or more pass/fail tests on-board the die. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，通过片上测试电路来评估集成电路中的模数转换。 例如，片上测试电路370可以表征数模转换的线性度和单调性之一或两者。 数字输入代码的转换输出的值可以与先前步骤的先前转换输出的值进行比较，以为扫描数字输入代码的每个步骤提供数字差值。 可以将数字差值与一个或多个预定限制进行比较，以在芯片上提供一个或多个通过/失败测试。 描述和要求保护其他实施例。
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公开(公告)号：US20230024662A1
公开(公告)日：2023-01-26
申请号：US17957217
申请日：2022-09-30
IPC分类号： H01L23/528 , H01L23/525 , H01L23/00 , H03K19/17736 , H01L25/065 , H03K19/1776
摘要： A die includes one or more power delivery layers to deliver power within the die. Additionally, the die also includes one or more transistor layers to at least partially implement a programmable fabric for the die. Furthermore, the die further includes one or more signal routing layers to transmit signals for use by the programmable fabric. Moreover, the one or more transistor layers physically separate the one or more power delivery layers from the one or more signal routing layers.
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公开(公告)号：US20220014202A1
公开(公告)日：2022-01-13
申请号：US17485119
申请日：2021-09-24
申请人： Rahul Pal , Dheeraj Subbareddy , Mahesh Kumashikar , Dheemanth Nagaraj , Rajesh Vivekanandham , Anshuman Thakur , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
发明人： Rahul Pal , Dheeraj Subbareddy , Mahesh Kumashikar , Dheemanth Nagaraj , Rajesh Vivekanandham , Anshuman Thakur , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
IPC分类号： H03K19/17796 , G06F15/78 , G06F30/34 , H03K19/17758
摘要： The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.
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公开(公告)号：US20110279149A1
公开(公告)日：2011-11-17
申请号：US12778874
申请日：2010-05-12
申请人： Atul Maheshwari
发明人： Atul Maheshwari
CPC分类号： H03K3/0315
摘要： An analog-to-digital converter (ADC) suitable for measuring on-die DC or low frequency analog voltages may include a ring oscillator having a group of circuit cells successively and circularly coupled. Under certain circumstances, the ring oscillator may produce an output frequency that corresponds substantially linear to the input voltage. Other embodiments may be disclosed or claimed.
摘要翻译： 适用于测量管芯直流或低频模拟电压的模数转换器（ADC）可包括环形振荡器，其具有连续且圆形耦合的一组电路单元。 在某些情况下，环形振荡器可产生与输入电压基本上线性相对应的输出频率。 可以公开或要求保护其他实施例。
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公开(公告)号：US20060221724A1
公开(公告)日：2006-10-05
申请号：US11094811
申请日：2005-03-31
申请人： Atul Maheshwari , Sanu Mathew , Mark Anders , Ram Krishnamurthy
发明人： Atul Maheshwari , Sanu Mathew , Mark Anders , Ram Krishnamurthy
IPC分类号： G11C7/06
CPC分类号： G06F9/3869 , G06F7/74
摘要： For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.
摘要翻译： 对于一个所公开的实施例，转换器将2个N位数据转换为指示具有预定逻辑值的数据中的位数的N位值。 转换器包括N个比较器，每个比较器确定具有预定逻辑值的数据中的位数是否超过多个参考值中的相应一个。 基于比较器的输出产生N位值。 对于另一个公开的实施例，第一延迟元件基于具有预定逻辑值的数据值中的位数来延迟信号，并且第二延迟元件基于具有预定逻辑的参考值中的位数来延迟该信号 值。 比较器然后基于延迟信号产生位值。
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