公开(公告)号：US07402854B2

公开(公告)日：2008-07-22

申请号：US11496120

申请日：2006-07-31

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

公开(公告)号：US5504828A

公开(公告)日：1996-04-02

申请号：US328291

申请日：1994-10-24

申请人： Michael F. Cina ,  Dennis L. Karst ,  Modest M. Oprysko ,  Mark B. Ritter ,  Jeannine M. Trewhella

发明人： Michael F. Cina ,  Dennis L. Karst ,  Modest M. Oprysko ,  Mark B. Ritter ,  Jeannine M. Trewhella

IPC分类号： G02B6/42 ,  G02B6/32

CPC分类号： G02B6/4204 ,  G02B6/4206

摘要： An optical fiber transmission apparatus for limiting the optical modes which were emitted from a source in such a way to impinge on an optical fiber to extract a high bandwidth from the fiber. The apparatus includes a lens or aperture to control the angle and distribution of light launched into the fiber. The apparatus achieves reproducibly high bandwidths in large core step-index optical fibers of short transmission length distances. The lens or aperture introduces light from the source into the fiber at an angle at which substantially no intermode delay occurs as the light propagates down the fiber. An integral fiber optic coupling assembly that includes an optical electronic component receptacle, the lens and/or aperture, and an optical fiber connector interface which provides low cost easy to manufacture assembly is also disclosed. A unitary plastic housing provides the function of a lens and mechanical reference or locating features for the light source and optical fiber.

摘要翻译： 一种光纤传输装置，用于限制从源发射的光模式以照射到光纤上以从光纤提取高带宽。 该装置包括用于控制发射到光纤中的光的角度和分布的透镜或孔。 该装置在具有短传输长度距离的大型核心阶跃折射率光纤中实现可重复的高带宽。 透镜或光圈将光从光源引入光纤，其角度基本上不发生模式间延迟，因为光沿着光纤传播。 还公开了一种包括光学电子部件插座，透镜和/或孔径以及提供低成本易于制造组装的光纤连接器接口的整体光纤耦合组件。 单一的塑料外壳提供了一个透镜的功能，并为光源和光纤提供机械参考或定位功能。

公开(公告)号：US08949685B2

公开(公告)日：2015-02-03

申请号：US12694829

申请日：2010-01-27

申请人： Douglas J. Joseph ,  Mark B. Ritter ,  José A. Tierno

发明人： Douglas J. Joseph ,  Mark B. Ritter ,  José A. Tierno

IPC分类号： G11C29/00 ,  H03M13/03 ,  G06F11/10 ,  G11C7/10

CPC分类号： H03M13/03 ,  G06F11/1028 ,  G11C7/1006 ,  G11C2207/104

摘要： Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.

摘要翻译： 公开了用于最小化与可单独访问的存储器件相关联的软错误的影响的技术。 作为示例，在由纠错码保护的存储器件的存储器阵列中组织列的方法包括通过使与存储器线相关联的存储器位之间的物理距离最大化来最大化纠错码的距离的步骤 在由纠错码保护的列内。 其他软错误保护技术可以包括使用前馈纠错码或使用存储器操作（例如，读或写操作）抑制和重试方法。

公开(公告)号：US08832010B2

公开(公告)日：2014-09-09

申请号：US13343371

申请日：2012-01-04

申请人： Bipin Rajendran ,  Mark B. Ritter

发明人： Bipin Rajendran ,  Mark B. Ritter

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/0635 ,  G06N3/04 ,  G06N3/049

摘要： According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

摘要翻译： 根据技术，电子设备被配置为对应于生物突触的特征。 电子装置包括平行布置的多个双极性电阻器以形成电子突触，连接到电子突触的一端和第一电子神经元的轴突连接，以及连接到电子突触的另一端的树突状连接和第二 电子神经元。 电子突触中突触传导的增加和减少是基于在低电阻状态和高电阻状态之间切换多个双极性电阻器的概率。

公开(公告)号：US07917799B2

公开(公告)日：2011-03-29

申请号：US11734375

申请日：2007-04-12

申请人： Lawrence Jacobowitz ,  Mark B. Ritter ,  Daniel J. Stigliani, Jr.

发明人： Lawrence Jacobowitz ,  Mark B. Ritter ,  Daniel J. Stigliani, Jr.

IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F1/00 ,  H03L7/099

CPC分类号： G06F1/10 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126

摘要： Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an output clock signal, which may be an analog signal at a variable frequency. Digital frequency control data are transmitted or distributed to the processor core; and that one processor core receives the digital frequency control data transmitted to the core, and uses that received digital frequency control data to set the frequency of the output clock signal of the clocking subsystem of the processor core. Preferably, multiple cores are asynchronously clocked and the core frequencies are independently set, and, there is no phase relationship between the core clocks.

摘要翻译： 公开了处理器核心中的数字频率时钟的方法和系统。 提供至少一个处理器核心，并且处理器核心具有用于产生输出时钟信号的时钟子系统，其可以是可变频率的模拟信号。 数字频率控制数据被发送或分发到处理器核心; 并且一个处理器核心接收发送到核心的数字频率控制数据，并且使用该接收到的数字频率控制数据来设置处理器核心的时钟子系统的输出时钟信号的频率。 优选地，多个核被异步计时，并且核心频率被独立设置，并且核心时钟之间没有相位关系。

公开(公告)号：US20080282074A1

公开(公告)日：2008-11-13

申请号：US11747300

申请日：2007-05-11

申请人： Lawrence Jacobowitz ,  Mark B. Ritter ,  Daniel J. Stigliani, JR.

发明人： Lawrence Jacobowitz ,  Mark B. Ritter ,  Daniel J. Stigliani, JR.

IPC分类号： G06F9/00

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F11/3442 ,  G06F2201/88 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/34

摘要： A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.

摘要翻译： 一种优化具有多个核心的多核芯片的性能的方法包括以下步骤：分别为多个核心中的每一个确定一个Vdd-frequency频率SCHMOO特性; 保存表示所述多个核心中的每一个的Vdd频率SCHMOO特性的数据; 基于所保存的数据，配置所述核以获得为给定工作负载提供至少一个最佳功耗和最佳性能的配置; 并且保存配置，使得可以在周期性和持续性的至少一个上更新和使用配置。

公开(公告)号：US20080165521A1

公开(公告)日：2008-07-10

申请号：US11621188

申请日：2007-01-09

申请人： KERRY BERNSTEIN ,  Paul William Coteus ,  Ibrahim (Abe) M. Elfadel ,  Philip George Emma ,  Kathryn W. Guarini ,  Thomas Fleischman ,  Allan Mark Hartstein ,  Ruchir Puri ,  Mark B. Ritter ,  Jeannine Madelyn Trewhella ,  Albert M. Young

发明人： KERRY BERNSTEIN ,  Paul William Coteus ,  Ibrahim (Abe) M. Elfadel ,  Philip George Emma ,  Kathryn W. Guarini ,  Thomas Fleischman ,  Allan Mark Hartstein ,  Ruchir Puri ,  Mark B. Ritter ,  Jeannine Madelyn Trewhella ,  Albert M. Young

IPC分类号： H05K7/00 ,  H01L21/50

CPC分类号： H01L24/83 ,  H01L21/6835 ,  H01L21/8221 ,  H01L24/26 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68354 ,  H01L2224/8385 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

摘要： A three-dimensional architecture chip includes a base chip including a unit integrated thereon and configured to perform electrical signal operations. An active layer is separately fabricated from the base layer. The active layer includes a component to service the unit of the base chip. The active layer is bonded to the base chip such that the component is aligned in vertical proximity of the unit. An electrical connection connects the unit to the component through vertical layers of at least one of the base chip and the active layer.

摘要翻译： 三维结构芯片包括基本芯片，其包括集成在其上并被配置为执行电信号操作的单元。 从基层分开制造有源层。 有源层包括用于服务于基片的单元的部件。 有源层被结合到基片，使得该元件在该单元的垂直方向上对准。 电连接通过基底芯片和有源层中的至少一个的垂直层将单元连接到部件。

公开(公告)号：US06507241B1

公开(公告)日：2003-01-14

申请号：US09678312

申请日：2000-10-03

申请人： Mark B. Ritter

发明人： Mark B. Ritter

IPC分类号： H03F102

CPC分类号： H03F3/45941

摘要： A circuit (and method) for correcting offset voltage in high-gain differential amplifier chains includes a detector element for detecting an offset voltage and a current mirror for generating an offset correction voltage. The circuit further has a current switch which outputs the offset correction voltage into the correct arm of the amplifier chain and a logic element which clocks the circuit, inputs a signal from the detector element and outputs a signal to the current switch.

摘要翻译： 用于校正高增益差分放大器链中的偏移电压的电路（和方法）包括用于检测偏移电压的检测器元件和用于产生偏移校正电压的电流镜。 电路还具有电流开关，其将偏移校正电压输出到放大器链的正确臂中，以及逻辑元件，其对电路进行计时，输入来自检测器元件的信号并向电流开关输出信号。

公开(公告)号：US20130173516A1

公开(公告)日：2013-07-04

申请号：US13343371

申请日：2012-01-04

申请人： Bipin Rajendran ,  Mark B. Ritter

发明人： Bipin Rajendran ,  Mark B. Ritter

IPC分类号： G06N3/063

CPC分类号： G06N3/0635 ,  G06N3/04 ,  G06N3/049

摘要： According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

公开(公告)号：US20130173515A1

公开(公告)日：2013-07-04

申请号：US13611722

申请日：2012-09-12

申请人： Bipin Rajendran ,  Mark B. Ritter

发明人： Bipin Rajendran ,  Mark B. Ritter

IPC分类号： G06N3/04

CPC分类号： G06N3/0635 ,  G06N3/04 ,  G06N3/049

摘要： According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

摘要翻译： 根据技术，电子设备被配置为对应于生物突触的特征。 电子装置包括平行布置的多个双极性电阻器以形成电子突触，连接到电子突触的一端和第一电子神经元的轴突连接，以及连接到电子突触的另一端的树突状连接和第二 电子神经元。 电子突触中突触传导的增加和减少是基于在低电阻状态和高电阻状态之间切换多个双极性电阻器的概率。