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222 条记录 (耗时 0.033 秒)

    Self-regulating voltage divider for series-stacked voltage rails
    7.
    发明授权
    Self-regulating voltage divider for series-stacked voltage rails 失效
    用于串联堆叠电压轨的自调节分压器

    公开(公告)号：US06509725B1

    公开(公告)日：2003-01-21

    申请号：US09683025

    申请日：2001-11-09

    申请人： Kerry Bernstein ,  Peter Edwin Cottrell ,  Roger Paul Gregor ,  Stephen V. Kosonocky ,  Edward Joseph Nowak

    发明人： Kerry Bernstein ,  Peter Edwin Cottrell ,  Roger Paul Gregor ,  Stephen V. Kosonocky ,  Edward Joseph Nowak

    IPC分类号： G05F304

    CPC分类号： G06F1/26

    摘要： A system and method for achieving self-regulated voltage division among multiple serially stacked voltage planes. The system of the present invention is incorporated within a source voltage plane having a source supply node for supplying current and a source ground node for sinking current supplied therefrom. An intermediate voltage supply node is coupled between the source supply voltage node and the source ground node for dividing the source voltage plane into a plurality of intermediate voltage planes. The self-regulated voltage divider of the present invention includes a first capacitor and a second capacitor that are each controllably coupled between either the source supply voltage node and the intermediate voltage supply node, or between the intermediate voltage supply node and the source ground node, such that a voltage level balance is achieved among the intermediate voltage planes.

    摘要翻译： 一种用于在多个串联电压平面之间实现自调节电压分配的系统和方法。 本发明的系统结合在具有用于提供电流的源电源节点的源极电压平面和用于吸收从其提供的电流的源极接地节点。 中间电压供应节点耦合在源电源电压节点和源极接地节点之间，用于将源极电压平面分成多个中间电压平面。 本发明的自调节分压器包括第一电容器和第二电容器，每个可控制地耦合在源电源电压节点和中间电压供应节点之间，或者在中间电压供应节点和源极接地节点之间， 使得在中间电压平面之间实现电压电平平衡。

    Body-contacted and double gate-contacted differential logic circuit and method of operation
    8.
    发明授权
    Body-contacted and double gate-contacted differential logic circuit and method of operation 有权
    身体接触和双门接触差分逻辑电路及其操作方法

    公开(公告)号：US06580293B1

    公开(公告)日：2003-06-17

    申请号：US09683325

    申请日：2001-12-14

    申请人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

    IPC分类号： H03K19096

    CPC分类号： H03K19/1737 ,  H03K3/356113 ,  H03K19/0963

    摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.

    摘要翻译： 设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。 逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。 在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。 在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。 结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。