公开(公告)号：US08053819B2

公开(公告)日：2011-11-08

申请号：US12120899

申请日：2008-05-15

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

摘要翻译： 具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

公开(公告)号：US20080023731A1

公开(公告)日：2008-01-31

申请号：US11496120

申请日：2006-07-31

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

摘要翻译： 具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

公开(公告)号：US20080203445A1

公开(公告)日：2008-08-28

申请号：US12120899

申请日：2008-05-15

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

摘要翻译： 具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

公开(公告)号：US07402854B2

公开(公告)日：2008-07-22

申请号：US11496120

申请日：2006-07-31

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

公开(公告)号：US20080259671A1

公开(公告)日：2008-10-23

申请号：US12127086

申请日：2008-05-27

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

IPC分类号： G11C5/02

CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/1052 ,  H01L2221/68359 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

摘要翻译： 其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个额外的分开的存储器阵列层。 对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。 优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。 所有层可以独立供电以提供额外的性能增强。

公开(公告)号：US07692944B2

公开(公告)日：2010-04-06

申请号：US12127086

申请日：2008-05-27

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

IPC分类号： G11C5/02

CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/1052 ,  H01L2221/68359 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

摘要翻译： 其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个额外的分开的存储器阵列层。 对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。 优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。 所有层可以独立供电以提供额外的性能增强。

公开(公告)号：US07408798B2

公开(公告)日：2008-08-05

申请号：US11278189

申请日：2006-03-31

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

IPC分类号： G11C5/02

CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/1052 ,  H01L2221/68359 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

摘要翻译： 其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个附加的独立存储器阵列层。 对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。 优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。 所有层可以独立供电以提供额外的性能增强。

公开(公告)号：US08452919B2

公开(公告)日：2013-05-28

申请号：US13567357

申请日：2012-08-06

申请人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

发明人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

IPC分类号： G06F13/00

CPC分类号： G11C7/1078 ,  G06F11/1028 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

摘要翻译： 具有改进性能，降低功耗和增加可靠性的高级内存。 存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路 对错误控制编码电路检测接收到的命令中的错误。 另一个存储器件包括可编程序序。 另一存储器件包括快速退出自刷新模式。 另一种存储装置包括由特征装置控制的自动刷新功能。 另一存储器件包括由存储器件的特性控制的自动刷新功能。

公开(公告)号：US08358522B2

公开(公告)日：2013-01-22

申请号：US12836933

申请日：2010-07-15

申请人： Paul W. Coteus ,  Andrew Ferencz

发明人： Paul W. Coteus ,  Andrew Ferencz

IPC分类号： H02M5/42

CPC分类号： H02M3/33592 ,  H02M2001/0048 ,  Y02B70/1475 ,  Y02B70/1491

摘要： An apparatus for providing synchronous rectifier gate drive timing is described. The apparatus includes circuitry to receive a first signal. The apparatus also includes circuitry to generate a second signal by modifying the first signal to delay a transition from high to low for a non-zero overlap duration. An output to apply an inverse of the first signal as a gate drive timing of at least a first transistor and to apply the second signal as a gate drive timing of at least a second transistor, where the first transistor is a part of a primary side of a full-bridge synchronous rectifier and the second transistor is a part of a secondary side of the full-bridge synchronous rectifier is also included. The second signal and the inverse of the first signal are high during the overlap duration. Methods and program storage devices are also disclosed.

摘要翻译： 描述了一种用于提供同步整流栅驱动定时的装置。 该装置包括用于接收第一信号的电路。 该装置还包括通过修改第一信号以在非零重叠持续时间内将从高转变为低的过渡来产生第二信号的电路。 用于将第一信号的反相作为至少第一晶体管的栅极驱动定时的输出，并施加第二信号作为至少第二晶体管的栅极驱动定时，其中第一晶体管是初级侧的一部分 的全桥同步整流器，而第二晶体管也是全桥同步整流二次侧的一部分。 第二信号和第一信号的反相在重叠期间是高的。 还公开了方法和程序存储装置。

公开(公告)号：US08343804B2

公开(公告)日：2013-01-01

申请号：US13364346

申请日：2012-02-02

申请人： Paul W. Coteus ,  Kyu-hyoun Kim

发明人： Paul W. Coteus ,  Kyu-hyoun Kim

IPC分类号： H01L21/00

CPC分类号： H01L24/73 ,  H01L23/481 ,  H01L24/06 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.

摘要翻译： 提供了一种用于实现用于存储器堆叠的多种不同类型的管芯的方法和结构。 普通晶片具有预定的掩模版类型。 标线型包括多个阵列和多个外围段。 多个通硅通孔（TSV）被放置在阵列和外围段之间的边界处。 基于从公共晶片选择划线的模具，获得用于存储器堆叠的多种不同类型的管芯。