-
1.发明授权Method of optimizing performance of multi-core chips and corresponding circuit and computer program product 有权优化多核芯片性能的方法及相应的电路及计算机程序产品公开(公告)号：US07917785B2
公开(公告)日：2011-03-29
申请号：US11747300
申请日：2007-05-11
CPC分类号： G06F1/3203 , G06F1/3243 , G06F11/3442 , G06F2201/88 , Y02D10/126 , Y02D10/152 , Y02D10/34
摘要： A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.
摘要翻译： 一种优化具有多个核心的多核芯片的性能的方法包括以下步骤：分别确定多个核心中的每一个的Vdd频率SCHMOO特性; 保存表示所述多个核心中的每一个的Vdd频率SCHMOO特性的数据; 基于所保存的数据，配置所述核以获得为给定工作负载提供至少一个最佳功耗和最佳性能的配置; 并且保存配置，使得其可以在周期性和持续性的至少一个上被更新和使用。
-
2.发明授权Method and apparatus for providing optoelectronic communication with an electronic device 有权用于与电子设备进行光电通信的方法和设备公开(公告)号：US07128472B2
公开(公告)日：2006-10-31
申请号：US10631933
申请日：2003-07-31
申请人： Alan F. Benner , Evan G. Colgan , How Tzu Lin , John H. Magerlein , Frank L. Pompeo , Subhash L. Shinde , Daniel J. Stigliani, Jr.
发明人： Alan F. Benner , Evan G. Colgan , How Tzu Lin , John H. Magerlein , Frank L. Pompeo , Subhash L. Shinde , Daniel J. Stigliani, Jr.
CPC分类号： G02B6/4201 , G02B6/4246 , G02B6/4249 , G02B6/4268 , G02B6/4281 , G02B6/4283 , G02B6/4292
摘要： An optoelectronic assembly for a computer system includes an electronic chip(s), a substrate, an electrical signaling medium, an optoelectronic transducer, and an optical coupling guide. The electronic chip(s) is in communication with the substrate, which is in communication with a first end of the electrical signaling medium. A second end of the electrical signaling medium is in communication with the optoelectronic transducer, and includes the optical coupling guide for aligning an optical signaling medium with the optoelectronic transducer. An electrical signal from the electronic chip is communicated to the optoelectronic transducer via the substrate and the electrical signaling medium. The optical transducer and electronic chip(s) share a common heat spreader, and communication to other groups of electronic chip(s) is done without the need for communication via a second level electrical package.
摘要翻译： 用于计算机系统的光电组件包括电子芯片，基板，电信号介质，光电转换器和光耦合引导件。 电子芯片与基板通信，该基板与电信号介质的第一端连通。 电信令介质的第二端与光电换能器通信，并且包括用于使光信号介质与光电换能器对准的光耦合引导件。 来自电子芯片的电信号通过衬底和电信令介质传送到光电换能器。 光学传感器和电子芯片共享共同的散热器，并且完成与其他电子芯片组的通信，而不需要通过第二级电气封装进行通信。
-
3.发明授权公开(公告)号：US07656789B2
公开(公告)日：2010-02-02
申请号：US11092033
申请日：2005-03-29
IPC分类号： H04L12/26
CPC分类号： H04L1/22
摘要： A system, method and storage medium for providing redundant I/O access between a plurality of interconnected processor nodes and I/O resources. The method includes determining whether a primary path between the interconnected processor nodes and the I/O resources is operational, where the primary path includes a first processor node and a primary multiplexer. If the primary path is operational, the transactions are routed via the primary path. If the primary path is not operational, the transactions are routed between the interconnected processor nodes and the I/O resources via an alternate path that includes a second processor node and an alternate multiplexer.
摘要翻译： 一种用于在多个互连的处理器节点和I / O资源之间提供冗余I / O访问的系统，方法和存储介质。 该方法包括确定互连处理器节点和I / O资源之间的主路径是否可操作，其中主路径包括第一处理器节点和主多路复用器。 如果主路径可操作，则通过主路径路由事务。 如果主路径不可操作，则经由包括第二处理器节点和替代多路复用器的备用路径在互连的处理器节点和I / O资源之间路由事务。
-
4.发明授权Methods and systems for a digital frequency locked loop for multi-frequency clocking of a multi-core processor 有权用于多核处理器多频时钟的数字锁频环路的方法和系统公开(公告)号：US07501865B1
公开(公告)日：2009-03-10
申请号：US11873462
申请日：2007-10-17
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/093 , H03L2207/50
摘要： A method and systems for a digital frequency locked loop in a multi-core processor are provided. The method includes applying a dither modulation signal at a dither modulation frequency to modulate an output frequency to provide a clock signal to a core of the multi-core processor. The method further includes filtering a feedback signal of the output frequency with respect to a target frequency. The method additionally includes determining a frequency error in the filtered feedback signal as a function of alignment of the output frequency to the target frequency, and adjusting the output frequency in response to the frequency error.
摘要翻译： 提供了一种用于多核处理器中数字频率锁定环路的方法和系统。 该方法包括以抖动调制频率应用抖动调制信号来调制输出频率以向多核处理器的核心提供时钟信号。 该方法还包括相对于目标频率对输出频率的反馈信号进行滤波。 该方法还包括根据输出频率与目标频率的对准确定滤波反馈信号中的频率误差，以及响应于频率误差调整输出频率。
-
公开(公告)号：US06963119B2
公开(公告)日：2005-11-08
申请号：US10250050
申请日：2003-05-30
IPC分类号： H01S5/022 , G02B6/43 , H01L31/0232 , H01S5/02 , H01S5/40 , H01S5/42 , H04B10/12 , H04B10/13 , H04B10/135 , H04B10/14
CPC分类号： H01S5/423 , G02B6/43 , H01L2224/16225 , H01S5/0224 , H01S5/02248 , H01S5/02256
摘要： An integrated optical transducer assembly includes a substrate and an optoelectronic array attached to the substrate. The optoelectronic array further includes a plurality of individual subunits bonded together to form a single array, with each of the subunits including a defined number of individual optoelectronic elements associated therewith. The elastomeric material maintains an original alignment between the plurality of subunits.
摘要翻译： 集成光学换能器组件包括衬底和附着到衬底的光电子阵列。 光电子阵列还包括多个单独的子单元，其结合在一起以形成单个阵列，其中每个子单元包括与其相关联的限定数量的单个光电元件。 弹性体材料保持多个子单元之间的原始对准。
-
6.发明授权High-density optoelectronic transceiver assembly for optical communication data links 有权用于光通信数据链路的高密度光电收发器组件公开(公告)号：US06789957B1
公开(公告)日：2004-09-14
申请号：US10250102
申请日：2003-06-04
IPC分类号： G02B600
CPC分类号： G02B6/43 , G02B6/4206
摘要： An optoelectronic transceiver assembly includes a plurality of optical transmission devices coupled to a first end of a multimode optical fiber core. Each of the plurality of optical transmission devices generates light at a different wavelength with respect to one another. A wavelength demultiplexing device is coupled to a second end of the multimode optical fiber core, and a plurality of optical detection devices is in proximity to the demultiplexing device. The optical detection devices receive light transmitted by the plurality of optical transmission devices.
摘要翻译： 光电收发器组件包括耦合到多模光纤芯的第一端的多个光传输装置。 多个光传输装置中的每一个相对于彼此产生不同波长的光。 波长解复用装置耦合到多模光纤核心的第二端，并且多个光学检测装置靠近解复用装置。 光检测装置接收由多个光传输装置发射的光。
-
7.发明授权公开(公告)号：US06752539B2
公开(公告)日：2004-06-22
申请号：US10185304
申请日：2002-06-28
IPC分类号： G02B636
CPC分类号： G02B6/43
摘要： An exemplary embodiment of the present invention is an apparatus for providing optical interprocessor communication. The apparatus comprises a multichip module and an optical module. The multichip module includes a substrate, an integrated circuit electrically connected to the substrate and a hermetically sealed cover. The hermetically sealed cover encloses a sealed portion of the substrate and the integrated circuit is inside of the sealed cover. The optical module includes an optical transceiver located on the substrate outside of the sealed portion and the optical transceiver is electrically connected to the integrated circuit through the substrate.
摘要翻译： 本发明的示例性实施例是一种用于提供光学处理器间通信的装置。 该装置包括多芯片模块和光学模块。 多芯片模块包括基板，电连接到基板的集成电路和密封的盖。 密封的盖子包围基板的密封部分，并且集成电路在密封盖的内部。 光学模块包括位于密封部分外部的基板上的光收发器，并且光收发器通过基板电连接到集成电路。
-
公开(公告)号：US4998792A
公开(公告)日：1991-03-12
申请号：US481083
申请日：1990-02-16
摘要： A fiber optic mode conditioner for obtaining an equilibrium light distribution in a multimode fiber optic link under test. Light is supplied to the link through a gap between two successive fiber optic segments, followed by a high-curvature region created by wrapping the second fiber optic segment around a mandrel. The gap functions as a mode filter, stripping off all but the lowest modes, while the curved region acts as a mode scrambler redistributing the light energy into the intermediate modes.
-
公开(公告)号：US08161314B2
公开(公告)日：2012-04-17
申请号：US11734334
申请日：2007-04-12
CPC分类号： G06F1/08 , G06F1/06 , H03L7/1976
摘要： A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequency. Digital frequency control data and an analog signal are both transmitted to that at least one processor core; and that processor core uses the received analog signal and digital frequency control data to set the frequency of the output clock signal of the clocking subsystem. In a preferred implementation, multiple cores are asynchronously clocked and the core frequencies are independently set.
摘要翻译： 公开了一种用于处理器核心中频率计时的方法和系统。 在该系统中，提供至少一个处理器核心，并且至少一个处理器核心具有用于以可变频率产生模拟输出时钟信号的时钟子系统。 数字频率控制数据和模拟信号都传送到该至少一个处理器核心; 并且处理器核心使用接收的模拟信号和数字频率控制数据来设置时钟子系统的输出时钟信号的频率。 在优选实施例中，多个核心被异步计时并且核心频率被独立设置。
-
10.发明授权All digital frequency-locked loop circuit method for clock generation in multicore microprocessor systems 失效用于多核微处理器系统中时钟产生的所有数字锁相环电路方法公开(公告)号：US07764132B2
公开(公告)日：2010-07-27
申请号：US12182204
申请日：2008-07-30
IPC分类号： H03K3/03
CPC分类号： H03L7/0996 , H03L7/18
摘要： A (DFLL) circuit residing on a local core of a multi-core microprocessor for generating a local core clock with a frequency for driving the local core includes a micro-controller configured to receive core characterizing digital data; a ring oscillator configured to generate the local core clock for the local core, and having a delay chain disposed between an output and a feedback input of the ring oscillator, the delay chain having delay taps each receiving the local core clock enabling quantum changes in the frequency of the local core clock; and a counter device configured to continually validate the frequency by generating a digital signal representative of the frequency to the micro-controller, the micro-controller compares the frequency of the local core clock to a desired clock frequency, and selects one of the delay taps based on the comparison to adjust the frequency value of the local core clock.
摘要翻译： 驻留在用于产生具有用于驱动本地核的频率的本地核心时钟的多核微处理器的本地核心上的（DFLL）电路包括被配置为接收核心表征数字数据的微控制器; 环形振荡器，其被配置为产生用于本地核心的本地核心时钟，并且具有设置在环形振荡器的输出和反馈输入之间的延迟链，所述延迟链具有每个接收本地核心时钟的延迟抽头，从而能够在 本地核心时钟频率; 以及配置为通过向微控制器生成表示频率的数字信号来连续验证频率的计数器装置，微控制器将本地核心时钟的频率与期望的时钟频率进行比较，并且选择延迟抽头之一 基于比较来调整本地核心时钟的频率值。
-
-
-
-
-
-
-
-
-
搜索结果
25 条记录 (耗时 0.019 秒)
