Abstract:
A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.
Abstract:
A method and apparatus configure a trusted domain and a plurality of isolated domains in a processor core. Each isolated domain is assigned a unique domain identifier. One or more resources are associated with each isolated domain. The associations are stored as permissions to access physical addresses of resources. Code to be executed by a hardware device is assigned to one of the isolated domains. The domain identifier for the assigned isolated domain is written to the hardware device. When the hardware device executes the code, each instruction is logically tagged with the domain identifier written to the hardware device. An instruction includes request to access a physical address. The hardware device compares the domain identifier of the instruction with the permissions. If the permissions allow the domain identifier to access the physical address, then access to the resource at the physical address is allowed. Access is otherwise blocked.
Abstract:
A wireless device dynamically programs a control register for a command-chain driven DMA device. The control register stores a beginning address of the linked list of commands and a secure bit. The secure bit is set if the transaction writing register is secure and a bit in the data being written into the register is set. DMA devices and other bus-mastering peripherals perform tasks described via a command chain that has access to secure resources when the processor is operating in the secure mode and the secure bit is set.
Abstract:
A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.
Abstract:
A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.
Abstract:
A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The spoke modules include a plurality of interface circuits each having a hardware address. A memory module stores the hub software and hub data and configuration data. The hub software includes a plurality of driver modules corresponding to the plurality of interface circuits. The processing module executes boot firmware to configure the plurality of driver modules based on the hardware address of each of the plurality of interface circuits.
Abstract:
In some embodiments, a method for supporting multiple devices on a high speed physical link may be described. An embedded device may assert a link request pin to request to transmit data on a multi-point communications link that may serve a plurality of embedded devices. A controlling device may receive the link request signal. When the controlling device finishes sending data on the link, it may address the plurality of embedded devices in a round robin format and may determine which device asserted the link request pin. The embedded device that asserted the link request pin may send an acknowledgement signal to the controlling device when it is addressed.
Abstract:
A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.
Abstract:
A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.