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公开(公告)号：US09600253B2
公开(公告)日：2017-03-21
申请号：US13444907
申请日：2012-04-12
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.
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22.发明授权Data parallel function call for determining if called routine is data parallel 失效数据并行功能调用，用于确定被调用的程序是否是数据并行的公开(公告)号：US08627043B2
公开(公告)日：2014-01-07
申请号：US13430168
申请日：2012-03-26
IPC分类号： G06F9/30
CPC分类号： G06F9/30072 , G06F8/456 , G06F9/30189 , G06F9/3851 , G06F9/3887
摘要： Mechanisms for performing data parallel function calls in code during runtime are provided. These mechanisms may operate to execute, in the processor, a portion of code having a data parallel function call to a target portion of code. The mechanisms may further operate to determine, at runtime by the processor, whether the target portion of code is a data parallel portion of code or a scalar portion of code and determine whether the calling code is data parallel code or scalar code. Moreover, the mechanisms may operate to execute the target portion of code based on the determination of whether the target portion of code is a data parallel portion of code or a scalar portion of code, and the determination of whether the calling code is data parallel code or scalar code.
摘要翻译： 提供了在运行期间执行代码中数据并行函数调用的机制。 这些机制可以操作以在处理器中执行具有对目标代码部分的数据并行函数调用的代码的一部分。 这些机制可以进一步操作以在运行时由处理器确定目标代码部分是代码的数据并行部分还是代码的标量部分，并确定调用代码是数据并行代码还是标量代码。 此外，这些机制可以基于代码的目标部分是代码的数据并行部分还是代码的标量部分的确定来执行代码的目标部分，以及确定调用代码是否是数据并行代码 或标量代码。
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公开(公告)号：US08627042B2
公开(公告)日：2014-01-07
申请号：US12649751
申请日：2009-12-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30072 , G06F8/456 , G06F9/30189 , G06F9/3851 , G06F9/3887
摘要： Mechanisms for performing data parallel function calls in code during runtime are provided. These mechanisms may operate to execute, in the processor, a portion of code having a data parallel function call to a target portion of code. The mechanisms may further operate to determine, at runtime by the processor, whether the target portion of code is a data parallel portion of code or a scalar portion of code and determine whether the calling code is data parallel code or scalar code. Moreover, the mechanisms may operate to execute the target portion of code based on the determination of whether the target portion of code is a data parallel portion of code or a scalar portion of code, and the determination of whether the calling code is data parallel code or scalar code.
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公开(公告)号：US20120198169A1
公开(公告)日：2012-08-02
申请号：US13442919
申请日：2012-04-10
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
CPC分类号： G06F9/3806 , G06F12/0875
摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.
摘要翻译： 提供了用于在代码的一部分中动态地重写分支指令的机制。 这些机制在代码的一部分中执行分支指令。 这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。 此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。 此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，机制将代码部分的执行重定向到指令高速缓存运行时系统。
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公开(公告)号：US08128498B2
公开(公告)日：2012-03-06
申请号：US11425452
申请日：2006-06-21
IPC分类号： A63F9/22
CPC分类号： G06N3/006 , A63F13/49 , A63F13/55 , A63F13/822 , A63F13/85 , A63F2300/537 , A63F2300/575 , G07F17/32
摘要： A mechanism is provided for configuring offline player behavior within a persistent world game. A player agent for an offline player includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game event occurs that triggers an offline player rule, the player agent may generate game events on behalf of the offline player. The player agent may also receive messages from an offline player. The messages may include commands for adding, removing, or editing offline player rules. A message may also include a command to view a list of rules or fire a one-time execution of a rule upon receipt. Therefore, a player may contribute to the persistent virtual world even when offline by sending commands using a messaging client or Web browser.
摘要翻译： 提供了一种用于在持久化世界游戏中配置离线玩家行为的机制。 用于离线播放器的播放器代理包括事件监视器，其监视由游戏服务器维护的持久虚拟世界中发生的事件。 当发生触发离线玩家规则的游戏事件时，玩家代理可以代表离线玩家生成游戏事件。 播放器代理也可以从离线播放器接收消息。 消息可能包括用于添加，删除或编辑离线播放器规则的命令。 消息还可以包括查看规则列表的命令或者在接收到一次规则执行时触发。 因此，即使当通过使用消息传递客户端或Web浏览器发送命令进行脱机时，玩家也可以对持久虚拟世界作出贡献。
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26.发明申请Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction 审中-公开动态重写缓存线驱逐响应中的分支指令公开(公告)号：US20110320786A1
公开(公告)日：2011-12-29
申请号：US12823226
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
CPC分类号： G06F8/4442 , G06F9/3806 , G06F12/0875 , G06F12/12
摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.
摘要翻译： 提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。 机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。 确定当前高速缓存行是否将从指令高速缓存中逐出。 处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。 此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。
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公开(公告)号：US07987464B2
公开(公告)日：2011-07-26
申请号：US11459669
申请日：2006-07-25
CPC分类号： G06F9/5077
摘要： A method, apparatus, and computer usable program code for logical partitioning and virtualization in heterogeneous computer architecture. In one illustrative embodiment, a portion of a first set of processors of a first type is allocated to a partition in a heterogeneous logically partitioned system and a portion of a second set of processors of a second type is allocated to the partition.
摘要翻译： 用于异构计算机体系结构中逻辑分区和虚拟化的方法，设备和计算机可用程序代码。 在一个说明性实施例中，第一类型的第一组处理器的一部分被分配给异构逻辑分区系统中的分区，并且第二类型的第二组处理器的一部分被分配给该分区。
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公开(公告)号：US08572359B2
公开(公告)日：2013-10-29
申请号：US12649860
申请日：2009-12-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3887 , G06F8/4441 , G06F9/381 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3859
摘要： Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The mechanisms further execute the first parallel execution group and determining, for each iteration in the subset of iterations, whether the iteration has a data dependence. Moreover, the mechanisms commit store data to system memory only for stores performed by iterations in the subset of iterations for which no data dependence is determined. Store data of stores performed by iterations in the subset of iterations for which a data dependence is determined is not committed to the system memory.
摘要翻译： 提供了在运行时提取数据依赖关系的机制。 所述机制执行具有循环的一部分代码，并为所述循环生成包括小于所述循环的总迭代次数的循环迭代子集的第一并行执行组。 机制进一步执行第一个并行执行组，并确定迭代子集中的每个迭代，迭代是否具有数据依赖性。 此外，机制仅将数据存储到系统存储器中，用于仅在确定了数据依赖性的迭代子集中通过迭代执行的存储。 在确定数据相关性的迭代子集中存储由迭代执行的存储数据不会提交给系统存储器。
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公开(公告)号：US20110320785A1
公开(公告)日：2011-12-29
申请号：US12823194
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
CPC分类号： G06F9/3806 , G06F12/0875
摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.
摘要翻译： 提供了用于在代码的一部分中动态地重写分支指令的机制。 这些机制在代码的一部分中执行分支指令。 这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。 此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。 此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，机制将代码部分的执行重定向到指令高速缓存运行时系统。
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公开(公告)号：US20110161642A1
公开(公告)日：2011-06-30
申请号：US12649805
申请日：2009-12-30
IPC分类号： G06F9/32
CPC分类号： G06F9/30076 , G06F9/325 , G06F9/3834 , G06F9/3838
摘要： Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor. Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.
摘要翻译： 提供了在运行时提取数据依赖关系的机制。 利用这些机制，执行具有循环的一部分代码。 为该循环生成第一个并行执行组，该组包括小于循环迭代总次数的循环迭代子集。 通过并行执行每个迭代来执行第一个并行执行组。 存储用于迭代的数据存储在处理器的相应存储高速缓存中。 处理器的依赖性检查逻辑为每次迭代确定迭代是否具有数据依赖性。 只有确定了没有数据依赖关系的商店的商店数据被提交到内存。
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