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公开(公告)号：US06901015B2
公开(公告)日：2005-05-31
申请号：US10463615
申请日：2003-06-18
申请人： Hirofumi Shinohara
发明人： Hirofumi Shinohara
CPC分类号： G11C29/808
摘要： A semiconductor memory device (1) comprises a normal RAM (2) and a redundancy RAM (3) provided independently from the normal RAM (2), serving as a redundancy circuit, and a control unit (4) for replacing a normal memory cell array of the normal RM (2) by a redundancy memory call array of the redundancy RAM (3). The control unit (4) can replace the normal memory cell array by some of a plurality of redundancy memory cells constituting the redundancy memory cell array. Therefore, a defective normal memory cell array can be replaced with using a redundancy memory cell which does not have a defect. As a result, a manufacturing yield of the semiconductor memory device (1) can be improved. With this constitution provided is a technique to improve the manufacturing yield of a semiconductor memory device which comprises a redundancy circuit.
摘要翻译： 一种半导体存储器件（1）包括与用作冗余电路的普通RAM（2）独立设置的正常RAM（2）和冗余RAM（3），以及用于替换正常存储器单元 通过冗余RAM（3）的冗余存储器调用阵列的正常RM（2）阵列。 控制单元（4）可以由构成冗余存储单元阵列的多个冗余存储单元中的一些代替正常存储单元阵列。 因此，可以使用不具有缺陷的冗余存储单元来替换有缺陷的正常存储单元阵列。 结果，可以提高半导体存储器件（1）的制造成品率。 提供这种结构是提高包括冗余电路的半导体存储器件的制造成品率的技术。
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公开(公告)号：US06590559B2
公开(公告)日：2003-07-08
申请号：US09293788
申请日：1999-04-20
IPC分类号： G09G336
CPC分类号： G09G3/3688
摘要： Wiring between output terminals of a source driver IC (output terminals of a TCP for source driver IC) and picture elements is equalized when number of the picture elements is not an integer multiplied by number of outputs of the source driver IC in the liquid crystal display. By giving a start pulse for indicating a start timing of drive sections to a predetermined drive section at a timing different from an originally set start timing, a part of output terminals of the drive section is made unavailable.
摘要翻译： 源极驱动器IC的输出端子（源极驱动器IC的TCP的输出端子）与像素之间的布线在液晶显示器的数量不是整数乘以源极驱动器IC的输出的整数时被均衡 。 通过在与原始设定的开始时刻不同的定时给出用于指示驱动部的开始定时的启动脉冲，驱动部的输出端的一部分不可用。
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公开(公告)号：US06320572B1
公开(公告)日：2001-11-20
申请号：US09168565
申请日：1998-10-09
IPC分类号： G09G506
CPC分类号： G09G3/3611 , G09G3/20 , G09G5/18
摘要： A control circuit for controlling a driving circuit that provides signals to a displaying means, wherein a function of outputting a plurality of digital signals at different phases is included, and said phases can be set by selective elements.
摘要翻译： 一种用于控制向显示装置提供信号的驱动电路的控制电路，其中包括以不同相位输出多个数字信号的功能，并且可以通过选择元件来设置所述相位。
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公开(公告)号：US5280201A
公开(公告)日：1994-01-18
申请号：US760997
申请日：1991-09-17
IPC分类号： G11C11/412 , G11C11/417 , H03K3/356 , H03K19/20 , H03K5/159
CPC分类号： H03K3/356165 , H03K3/356147
摘要： A semiconductor logic circuit apparatus which include a first switching element consisting of a field effect transistor for changing holding data, an inverter circuit whose input is connected with one end of the first switching element, a feedback circuit whose input and output are connected with the output and input of the inverter circuit, and a second switching element connected between the output of the feedback circuit and first or second potential. The second switching element is effective for enabling and disabling the feedback circuit.The first and second switching elements are opened/closed in reverse phase to each other. Feedback of the feedback circuit is prevented until the inverter circuit is driven from its "0" to its "1" holding state, so that driving of the inverter circuit becomes easy and operational stability and operating speed are enhanced.
摘要翻译： 一种半导体逻辑电路装置，包括由用于改变保持数据的场效应晶体管组成的第一开关元件，其输入端与第一开关元件的一端连接的反相器电路，其输入和输出与输出端连接的反馈电路 逆变器电路的输入以及连接在反馈电路的输出与第一或第二电位之间的第二开关元件。 第二开关元件对于启用和禁用反馈电路是有效的。 第一和第二开关元件以相反的方式彼此打开/关闭。 反馈电路的反馈被阻止，直到逆变器电路从其“0”驱动到“1”保持状态，使得逆变器电路的驱动变得容易，并且提高了操作稳定性和操作速度。
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公开(公告)号：US20090141569A1
公开(公告)日：2009-06-04
申请号：US12367871
申请日：2009-02-09
IPC分类号： G11C11/416 , G11C5/14 , G11C7/00 , G11C8/00
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。
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公开(公告)号：US20090101977A1
公开(公告)日：2009-04-23
申请号：US12253563
申请日：2008-10-17
申请人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
发明人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
IPC分类号： H01L47/00 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/28035 , H01L21/3081 , H01L21/3086 , H01L21/321 , H01L29/785
摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.
摘要翻译： 本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。 本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极， 翅片状半导体部分，其间具有栅极绝缘膜。 解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。
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公开(公告)号：US20060241276A1
公开(公告)日：2006-10-26
申请号：US10524636
申请日：2003-08-29
IPC分类号： C08G14/02
摘要： A phenolic novolak having the contents of a monomeric phenol and a dimeric phenol and a degree of dispersion controlled can be obtained in high yield by a process for production of a phenolic novolak having a step of conducting a heterogeneous reaction of a phenol and an aldehyde in the presence of a phosphoric acid and an unreactive oxygen-containing organic solvent as a reaction cosolvent.
摘要翻译： 通过具有进行苯酚和醛的非均相反应的酚醛清漆的制造方法，可以高收率地获得具有单体苯酚和二聚苯酚含量的苯酚酚醛清漆和分散度控制的酚醛清漆 存在磷酸和不含活性的含氧有机溶剂作为反应助溶剂。
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公开(公告)号：US07003622B2
公开(公告)日：2006-02-21
申请号：US10167087
申请日：2002-06-12
IPC分类号： G06F12/00
CPC分类号： G11C29/84 , G11C29/80 , G11C29/808
摘要： A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the regular RAM can be replaced, and a control block for selecting either at least the regular RAM or the redundant RAM according to an address applied thereto, and for reading data from a memory cell of the selected RAM specified by the address. A plurality of regular RAMs can be disposed and the redundant RAM includes redundant memory elements by which defective memory elements of an arbitrary one of the plurality of regular RAMs can be replaced. The control block selects either one of the plurality of regular RAMs or the redundant RAM according to an address applied thereto, and reads data from a memory cell of the selected RAM specified by the address.
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公开(公告)号：US5384734A
公开(公告)日：1995-01-24
申请号：US956137
申请日：1992-10-02
IPC分类号： G11C11/401 , G11C8/16 , G11C7/00
CPC分类号： G11C8/16
摘要： Memory cell array includes a plurality of 2-port memory cells. A first row address decoder for decoding a first address signal to select a first word line included in any one of a plurality of word line groups, and a second row address decoder for decoding a second address signal to select a second word line included in any one of a plurality of word line groups are provided. A word line driving circuit receives output signals of first and second row address decoders to drive first and second word lines in accordance with a predetermined inhibit condition.
摘要翻译： 存储单元阵列包括多个2端口存储单元。 第一行地址解码器，用于解码第一地址信号以选择包括在多个字线组中的任一个中的任何一个字线组中的第一字线;以及第二行地址解码器，用于解码第二地址信号以选择任何 提供多个字线组中的一个。 字线驱动电路接收第一和第二行地址解码器的输出信号，以根据预定的禁止条件驱动第一和第二字线。
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公开(公告)号：US5177706A
公开(公告)日：1993-01-05
申请号：US666518
申请日：1991-03-11
CPC分类号： G11C8/16
摘要： A semiconductor memory device includes a plurality of ports enabling simultaneous writing and reading of data of M words.times.N bits. A plurality of memory cells are arranged in (M/n) rows.times.(n.times.N) columns in a memory call array, write and read word lines are commonly connected to the memory cells of one row, and write column selecting line are connected to every n (the number of words) memory cells of the memory cells of one row. Write and read bit lines are connected to the memory cells of one column. Data is input to the write bit line from an input terminal through a write circuit. and data read from the memory cell is output to an output terminal through a sense amplifier. A first port is formed by the write word lines, the write column selecting lines, the write bit lines and the input terminal, and a second port is formed by the read word lines, read bit lines and the output terminal. M, N and n are natural numbers and M, N.gtoreq.n.
摘要翻译： 半导体存储器件包括多个端口，能够同时写入和读取M字×N位的数据。 多个存储单元以存储器调用阵列中的（M / n）行x（n×N）列排列，写入和读取字线通常连接到一行的存储单元，并且写列选择线连接到每n个 （单词数）一行存储单元的存储单元。 写和读位线连接到一列的存储单元。 数据通过写入电路从输入端输入写入位线。 并且从存储单元读取的数据通过读出放大器输出到输出端。 第一端口由写字线，写列选择线，写位线和输入端形成，第二端口由读字线，读位线和输出端形成。 M，N和n是自然数，M，N> / = n。
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