摘要:
A semiconductor logic circuit apparatus which include a first switching element consisting of a field effect transistor for changing holding data, an inverter circuit whose input is connected with one end of the first switching element, a feedback circuit whose input and output are connected with the output and input of the inverter circuit, and a second switching element connected between the output of the feedback circuit and first or second potential. The second switching element is effective for enabling and disabling the feedback circuit.The first and second switching elements are opened/closed in reverse phase to each other. Feedback of the feedback circuit is prevented until the inverter circuit is driven from its "0" to its "1" holding state, so that driving of the inverter circuit becomes easy and operational stability and operating speed are enhanced.
摘要:
A semiconductor memory device includes a plurality of ports enabling simultaneous writing and reading of data of M words.times.N bits. A plurality of memory cells are arranged in (M/n) rows.times.(n.times.N) columns in a memory call array, write and read word lines are commonly connected to the memory cells of one row, and write column selecting line are connected to every n (the number of words) memory cells of the memory cells of one row. Write and read bit lines are connected to the memory cells of one column. Data is input to the write bit line from an input terminal through a write circuit. and data read from the memory cell is output to an output terminal through a sense amplifier. A first port is formed by the write word lines, the write column selecting lines, the write bit lines and the input terminal, and a second port is formed by the read word lines, read bit lines and the output terminal. M, N and n are natural numbers and M, N.gtoreq.n.
摘要:
Test data stored in a data register 13a are applied to a data generator 11a and compared with a 1 bit signal stored in a scan latch 1c to determine the coincidence or non-coincidence therebetween. Outputs from the data generator 11a are applied to RAM 10 to be written in a designated region in a memory cell array 6. Data read from the said region of the memory cell array 6 are compared with expected value data in a comparator 12. Thus, the collation of data is carried out.
摘要:
MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
摘要:
An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.
摘要:
A machining method of a press die having a pierce cutter and a secondary relief-clearance area recessed inward relative to a profile of the pierce cutter is provided. A plunge cutting tool having a tool body and at least one edge portion provided on an outer circumference of an end of the tool body is used, the edge portion being protruding from the outer circumference of the tool body and being capable of carving while rotating around an axis of the tool body and moving in an axial direction of the tool body. While rotating the plunge cutting tool with an axis of the tool body being approximately parallel to a surface of the pierce cutter, the plunge cutting tool is relatively moved along the profile of the pierce cutter. The plunge cutting tool is also relatively moved in the axial direction of the tool body along the shape of the pierce cutter and the secondary relief-clearance area in a piercing direction each time the plunge cutting tool is relatively moved by a predetermined pitch.
摘要:
A manufacturing method for a semiconductor device permits a MOSFET with a pocket layer to be securely formed even when microminiaturization makes it difficult to implant impurity ions at an angle with respect to a silicon substrate in manufacturing a semiconductor, a MOSFET having a pocket layer in particular. A gate electrode composed of a gate oxide film, a poly-silicon, and a tungsten silicide, and a nitride film pattern are selectively formed on a p-type silicon substrate, then p-type impurity ions are implanted perpendicularly to the p-type silicon substrate. A p-type ion implantation region formed by implanting the p-type impurity ions is diffused for activation to thereby form a pocket layer before another ion implantation region is formed.
摘要:
A module cell generating device of a semiconductor integrated circuit includes a parameter input part for applying a designation parameter, a basic cell group storing the basic cells, and a basic cell arranging and wiring process part for generating layout designing data by utilizing a structure description part which is a control description for defining the arrangement method and the wiring method of the basic cells, the designation parameter, the structure description, and the basic cells. Furthermore, it includes a basic cell generating process part for generating the newly designated basic cells in accordance with the designation parameter.
摘要:
A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.
摘要:
A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines of low resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.