公开(公告)号：US20090089503A1

公开(公告)日：2009-04-02

申请号：US12204315

申请日：2008-09-04

申请人： Masahiro YOSHIDA ,  Yasuhito Arikawa

发明人： Masahiro YOSHIDA ,  Yasuhito Arikawa

IPC分类号： G06F12/00

CPC分类号： G06F11/008 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/3409 ,  G06F11/3485 ,  G06F2201/81 ,  G06F2201/88

摘要： A disk array apparatus has a plurality of disks constituting a mounted RAID group and controls access from an upper-level device to each of the disks. The disk array apparatus also has a performance information collector for collecting a piece of performance-related information of each of the disks, and a suspected disk detector for comparing the pieces of information collected for the disks by the performance information collector among disks constituting a single one of the RAID group and detecting a suspected disk suspected of being abnormal in performance based on a result of the comparison.

摘要翻译： 磁盘阵列装置具有构成安装的RAID组的多个磁盘，并且控制从上级装置到每个磁盘的访问。 磁盘阵列装置还具有用于收集每个磁盘的性能相关信息的性能信息收集器，以及可疑磁盘检测器，用于将构成单个磁盘的磁盘之间的性能信息收集器的磁盘收集的信息进行比较 其中一个RAID组，并根据比较结果检测疑似性能异常的可疑磁盘。

公开(公告)号：US20110079252A1

公开(公告)日：2011-04-07

申请号：US12897384

申请日：2010-10-04

申请人： Junya MINAMIDA ,  Issei UEDA ,  Yasuhiro CHOUNO ,  Osamu KURODA ,  Kazuyoshi ESHIMA ,  Masahiro YOSHIDA ,  Satoshi MORITA

发明人： Junya MINAMIDA ,  Issei UEDA ,  Yasuhiro CHOUNO ,  Osamu KURODA ,  Kazuyoshi ESHIMA ,  Masahiro YOSHIDA ,  Satoshi MORITA

IPC分类号： B08B3/00

CPC分类号： H01L21/67051 ,  H01L21/6708 ,  H01L21/67178 ,  H01L21/6719 ,  H01L21/67196 ,  Y10S414/135

摘要： Provided is a substrate processing apparatus wherein, even if a trouble occurs, it is bound to continue a process for the substrate without stopping the substrate processing apparatus entirely. The substrate processing apparatus according to the present disclosure includes first and second substrate conveying devices configured to convey wafers, and first and second processing blocks provided on the right and left sides of the substrate conveying device and having processing unit arrays each configured to perform the same process. Processing unit arrays on one side and processing unit arrays on the other side are respectively connected to a processing liquid supply system commonly provided with them. And, when any one of substrate conveying devices, processing liquid supply systems has a problem, the process for the wafer can be performed in the processing unit array to which the substrate conveying device and the processing liquid supply system under normal operation belong.

摘要翻译： 提供了一种基板处理装置，其中即使发生故障，也必须在不停止基板处理装置的情况下继续进行基板的处理。 根据本公开的基板处理装置包括被配置为输送晶片的第一和第二基板输送装置，以及设置在基板输送装置的左侧和左侧的第一和第二处理块，并且具有各自被配置为执行相同的处理单元阵列 处理。 一侧的处理单元阵列和另一侧的处理单元阵列分别连接到通常设置有它们的处理液体供应系统。 并且，当基板输送装置中的任一个处理液供给系统存在问题时，可以在基板输送装置和处理液供给系统正常运转所属的处理单元阵列中进行晶片的处理。

公开(公告)号：US20100295593A1

公开(公告)日：2010-11-25

申请号：US12772667

申请日：2010-05-03

申请人： Masahiro YOSHIDA

发明人： Masahiro YOSHIDA

IPC分类号： H03H11/26

CPC分类号： H03H11/265

摘要： A delay circuit (100) includes capacitor elements constituted of nMOS transistors (141, 142) between an input inverter circuit (110) and an output inverter circuit (120). The input inverter circuit (110) includes a pMOS transistor (PM1) and an nMOS transistor (NM1) that are directly connected between a power source potential (VDD) and a ground potential (VSS) through a resistor (R1). Between a signal line (130) and the gate of the nMOS transistor (141), and between the signal line (130) and the gate of the nMOS transistor (142), pMOS transistors (151, 152) are provided, respectively. In this structure, in the case where an input signal is changed from L to H, the PVT sensitivity of a delay circuit is automatically alleviated. As a result, the PVT sensitivity is automatically alleviated.

摘要翻译： 延迟电路（100）包括在输入反相器电路（110）和输出反相器电路（120）之间由nMOS晶体管（141,142）构成的电容器元件。 输入逆变器电路（110）包括通过电阻（R1）直接连接在电源电位（VDD）和接地电位（VSS）之间的pMOS晶体管（PM1）和nMOS晶体管（NM1）。 在信号线（130）和nMOS晶体管（141）的栅极之间以及在信号线（130）和nMOS晶体管（142）的栅极之间分别提供pMOS晶体管（151,152）。 在这种结构中，在输入信号从L变为H的情况下，延迟电路的PVT灵敏度被自动减轻。 结果，PVT灵敏度自动减轻。

公开(公告)号：US20070243684A1

公开(公告)日：2007-10-18

申请号：US11767074

申请日：2007-06-22

申请人： Nobuyuki KATSUKI ,  Atsushi OGA ,  Shuuichi SENOU ,  Noriyuki OTA ,  Masahiro YOSHIDA ,  Kenta ARAI ,  Atsushi NAKAGAWA ,  Tomotaka MURAKAMI

发明人： Nobuyuki KATSUKI ,  Atsushi OGA ,  Shuuichi SENOU ,  Noriyuki OTA ,  Masahiro YOSHIDA ,  Kenta ARAI ,  Atsushi NAKAGAWA ,  Tomotaka MURAKAMI

IPC分类号： H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L29/1045

摘要： The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A semiconductor element of the circuit different from the reference voltage generator circuit has a channel region where a substrate impurity concentration is higher than in other part of the region at least in the drain region.

摘要翻译： 半导体器件包括参考电压发生器电路和与参考电压发生器电路不同的电路。 参考电压发生器电路的半导体元件具有至少在漏极区附近衬底杂质浓度基本均匀的沟道区。 与参考电压发生器电路不同的电路的半导体元件具有至少在漏极区域中衬底杂质浓度高于该区域的其它部分的沟道区域。