公开(公告)号：US10418002B2

公开(公告)日：2019-09-17

申请号：US15786240

申请日：2017-10-17

申请人： MEDIATEK INC.

发明人： Ping Chao ,  Ting-An Lin ,  Tung-Hsing Wu ,  Kung-Tsun Yang ,  Wan-Yu Chen ,  Chuang-Chi Chiou ,  Ping-yao Wang ,  Wei-Gen Wu ,  Hsin-Hao Chung ,  Chih-Ming Wang ,  Han-Liang Chou ,  Chung Hsien Lee ,  Yung-Chang Chang ,  Chi-Cheng Ju

IPC分类号： G09G5/393 ,  G09G5/395 ,  H04N19/423 ,  G09G5/39 ,  H04N19/426 ,  H04N19/39 ,  H04N19/59 ,  G06F13/16 ,  H04N1/32

摘要： Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.

公开(公告)号：US20190281312A1

公开(公告)日：2019-09-12

申请号：US16293647

申请日：2019-03-06

申请人： MEDIATEK INC.

发明人： Chi-Min Chen ,  Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC分类号： H04N19/186 ,  H04N19/182 ,  H04N19/119 ,  H04N19/157 ,  H04N19/44 ,  H04N19/91

摘要： A palette decoding apparatus includes a palette color storage device which stores palette colors, a color index storage device which stores color indices of pixels, and a palette value processing circuit which generates a palette value for each pixel by reading data from the color index storage device and the palette color storage device. A frame is divided into first coding units, and each first coding unit is sub-divided into one or more second coding units. Before a palette value of a last pixel in a first coding unit is generated by the palette value processing circuit, a palette value of a non-last pixel in the first coding unit is generated by the palette value processing circuit and used by a reconstruction circuit of the video decoder.

公开(公告)号：US10250912B2

公开(公告)日：2019-04-02

申请号：US15016221

申请日：2016-02-04

申请人： MEDIATEK INC.

发明人： Chia-Yun Cheng ,  Yung-Chang Chang

IPC分类号： H04N19/91

摘要： An apparatus is capable of achieving high-throughput entropy decoding, and includes an arithmetic decoding processing circuitry and a variable-length decoder (VLD). The arithmetic decoding processing circuitry receives a video bitstream through a bitstream input, applies arithmetic decoding to at least a portion of the video bitstream to derive one or more arithmetic-decoded binary strings containing no arithmetic encoded binary string, and stores the arithmetic-decoded binary strings in the storage device. The variable-length decoder is coupled to the arithmetic decoding processing circuitry, the storage device and a VLD output. The variable-length decoder receives at least a portion of arithmetic-decoded bitstream when arithmetic-decoded bitstreams stored in the storage device are complete for a selected image unit, decodes at least a portion of arithmetic-decoded bitstream into one or more decoded syntax elements, and provides the decoded syntax elements through the VLD output.

公开(公告)号：US10237554B2

公开(公告)日：2019-03-19

申请号：US15273733

申请日：2016-09-23

申请人： MEDIATEK INC.

发明人： Yung-Chang Chang ,  Chi-Cheng Ju ,  Yi-Hau Chen ,  De-Yuan Shen

IPC分类号： H04N19/124 ,  H04N19/91 ,  H04N19/174 ,  H04N19/423 ,  H04N19/436 ,  H04N19/13 ,  H04N19/152 ,  H04N19/184 ,  H04N19/61

摘要： A method and apparatus for video encoding to generate a partitioned bitstream without buffering transform coefficient and/or prediction data for subsequent coding units are disclosed. An encoder incorporating an embodiment according to the present invention receives first video parameters associated with a current coding unit, wherein no first video parameters associated with subsequent coding units are buffered. The encoder then encodes the first video parameters to generate a current first compressed data corresponding to the current coding unit. A first memory address in the first logic unit is determined and the encoder provides the current first compressed data at the first memory address in the first logic unit.

公开(公告)号：US10171824B2

公开(公告)日：2019-01-01

申请号：US15638888

申请日：2017-06-30

申请人： MEDIATEK INC.

发明人： Tsu-Ming Liu ,  Yung-Chang Chang ,  Chi-Cheng Ju

IPC分类号： H04N19/44 ,  H04N19/61 ,  H04N19/105 ,  H04N19/156 ,  H04N19/159 ,  H04N19/172 ,  H04N19/426

摘要： Method and system of video decoding incorporating frame compression to reduce frame buffer size are disclosed. The method adjusts parameters of the frame compression according to decoder system information or syntax element in the video bitstream. The decoder system information may be selected from a group consisting of system status, system parameter and a combination of system status and system parameter. The decoder system information may include system bandwidth, frame buffer size, frame buffer status, system power consumption, and system processing load. The syntax element comprises reference frame indicator, initial picture QP (quantization parameter), picture type, and picture size. The adaptive frame compression may be applied to adjust compression ratio. Furthermore, the adaptive frame compression may be applied to a decoder for a scalable video coding system or a multi-layer video coding system.

公开(公告)号：US10123044B2

公开(公告)日：2018-11-06

申请号：US15209765

申请日：2016-07-14

申请人： MEDIATEK INC.

发明人： Min-Hao Chiu ,  Yu-Chuan Wang ,  Yung-Chang Chang

IPC分类号： H04N19/60 ,  H04N19/12 ,  H04N19/62 ,  H04N19/88 ,  H04N19/547

摘要： A partial decoding circuit with inverse second transform has a transpose buffer, a first-direction inverse residual transform circuit, and a second-direction inverse residual transform circuit. The transpose buffer stores an intermediate inverse residual transform result. The first-direction inverse residual transform circuit processes an inverse quantization output to generate the intermediate inverse residual transform result to the transpose buffer. The second-direction inverse residual transform circuit accesses the transpose buffer to retrieve the intermediate inverse residual transform result, and processes the intermediate inverse residual transform result to generate a final inverse residual transform result, where the final inverse residual transform result of the inverse second transform is further processed by an inverse transform circuit. The first-direction inverse residual transform circuit and the second-direction inverse residual transform circuit process partial residual transform data of different process units in a parallel processing manner.

公开(公告)号：US20180249175A1

公开(公告)日：2018-08-30

申请号：US15964059

申请日：2018-04-26

申请人： MEDIATEK INC.

发明人： Shun-Hsiang Chuang ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC分类号： H04N19/577 ,  H04N19/52 ,  H04N19/176 ,  H04N19/105 ,  H04N19/58 ,  H04N19/96

CPC分类号： H04N19/577 ,  H04N19/105 ,  H04N19/176 ,  H04N19/52 ,  H04N19/58 ,  H04N19/96

摘要： A method for motion vector predictor derivation of a block includes scanning a plurality of candidate motion vector predictors derived from at least a portion of neighbors of the block. The step of scanning the candidate motion vector predictors includes: regarding one of the candidate motion vector predictors, selectively updating a first predictor list according to the candidate motion vector predictor when the candidate motion vector predictor points to a reference block in a designated reference frame of the block, and selectively updating a second predictor list according to the candidate motion vector predictor when the candidate motion vector predictor points to a reference block in a specific reference frame different from the designated reference frame of the block.

公开(公告)号：US20180020228A1

公开(公告)日：2018-01-18

申请号：US15644815

申请日：2017-07-09

申请人： MEDIATEK INC.

发明人： Ming-Long Wu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC分类号： H04N19/44 ,  H04N19/91 ,  H04N19/70

CPC分类号： H04N19/44 ,  H04N19/436 ,  H04N19/70 ,  H04N19/91

摘要： A video processing system includes a storage device, a demultiplexing circuit, and a syntax parser. The storage device includes a first buffer and a second buffer. The demultiplexing circuit performs a demultiplexing operation upon an input bitstream to write a video bitstream into the first buffer and write start points of bitstream segments of the video bitstream stored in the first buffer into the second buffer. Each start point is indicative of a start address of a corresponding bitstream segment stored in the first buffer. The syntax parser includes syntax parsing circuits and a syntax parsing control circuit. The syntax parsing control circuit fetches a start point from the second buffer, assigns the fetched start point to a syntax parsing circuit, and triggers the selected syntax parsing circuit to start syntax parsing of a bitstream segment that is read from the first buffer according to the fetched start point.

公开(公告)号：US20170353738A1

公开(公告)日：2017-12-07

申请号：US15615845

申请日：2017-06-07

申请人： MEDIATEK INC.

发明人： Min-Hao Chiu ,  Yung-Chang Chang

IPC分类号： H04N19/88 ,  H04N19/436 ,  H04N19/91 ,  H04N19/82

CPC分类号： H04N19/88 ,  H04N19/129 ,  H04N19/18 ,  H04N19/436 ,  H04N19/82 ,  H04N19/91

摘要： A coefficient access method includes: receiving a coefficient generated from an entropy decoding process, wherein the received coefficient is a part of a transform block (TB); before the received coefficient is stored into an inverse scan (IS) storage device, determining a storage position of the received coefficient according to a transpose flag associated with the TB, wherein the transpose flag indicates whether or not a coefficient transpose process is needed; and after the storage position is determined, storing the received coefficient into the determined storage position in the IS storage device.

公开(公告)号：US20170251218A1

公开(公告)日：2017-08-31

申请号：US15438774

申请日：2017-02-22

申请人： MEDIATEK INC.

发明人： Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC分类号： H04N19/44 ,  H04N19/129 ,  H04N19/436 ,  H04N19/124 ,  H04N19/60

CPC分类号： H04N19/436 ,  H04N19/61

摘要： A residual processing circuit has a single-path pipeline and a single-path controller. The single-path pipeline has an inverse scan (IS) circuit, an inverse quantization (IQ) circuit and an inverse transform (IT) circuit arranged to process a current non-zero residual data block in a pipeline manner. The current non-zero residual data block is at least a portion of a transform unit. The single-path controller controls pipelined processing of the current non-zero residual data block at the single-path pipeline. The single-path controller instructs the IS circuit to start IS processing of a next non-zero residual data block before the IT circuit finishes a first half of IT processing of the current non-zero residual data block.