公开(公告)号：US10884659B2

公开(公告)日：2021-01-05

申请号：US16023177

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A timer of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.

公开(公告)号：US10776201B2

公开(公告)日：2020-09-15

申请号：US16236094

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/10 ,  H03M13/29

Abstract: Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.

公开(公告)号：US10733104B2

公开(公告)日：2020-08-04

申请号：US16054096

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/08 ,  G06F12/0866 ,  G06F12/0804 ,  G06F13/12 ,  G06F9/445 ,  G06F1/24 ,  G06F13/38

Abstract: Techniques are disclosed herein for providing accelerated recovery techniques of a memory device. Such techniques can allow for recovery of the memory device, such as, but not limited to, a flash memory device, following an unexpected reset event.

公开(公告)号：US20200210279A1

公开(公告)日：2020-07-02

申请号：US16237263

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Jonathan Parry ,  Nadav Grosz ,  David Aaron Palmer ,  Christian M. Gyllenskog

IPC: G06F11/10 ,  G06F12/02 ,  G06F3/06

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

公开(公告)号：US20200065256A1

公开(公告)日：2020-02-27

申请号：US16113014

申请日：2018-08-27

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/10 ,  G06F17/30

Abstract: Aspects of the present disclosure configure a memory sub-system to map logical memory addresses to physical memory addresses using a tree data structure in the memory sub-system. For example, a memory sub-system controller of the memory sub-system can generate a tree data structure on cache memory to cache, from non-volatile memory, at least one portion of mapping data, where the non-volatile memory is implemented by a set of memory components separate from the cache memory. The mapping data, stored on the non-volatile memory, can map a set of logical memory addresses to a corresponding set of physical memory addresses of the non-volatile memory, and a node of the tree data structure can comprise node data that describes a memory area of the non-volatile memory where data is written across a sequence of contiguous physical memory addresses.

公开(公告)号：US10573391B1

公开(公告)日：2020-02-25

申请号：US16208165

申请日：2018-12-03

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/12 ,  G11C16/16 ,  G11C16/08 ,  G06F3/06 ,  G11C7/10

Abstract: Devices and techniques for enhanced flush transfer efficiency via flush prediction in a storage device are described herein. User data from a user data write can be stored in a buffer. The size of the user data stored in the buffer can be smaller than a write width for a storage device subject to the write. This size difference results in buffer free space. A flush trigger can be predicted. Additional data can be marshalled in response to the prediction of the flush trigger. The size of the additional data is less than or equal to the buffer free space. The additional data can be stored in the buffer free space. The contents of the buffer can be written to the storage device in response to the flush trigger.

公开(公告)号：US20240385961A1

公开(公告)日：2024-11-21

申请号：US18664142

申请日：2024-05-14

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/02 ,  G06F12/0891

Abstract: Methods, systems, and devices for valid data identification for garbage collection are described. In connection with writing data to a block of memory cells, a memory system may identify a portion of a logical address space that includes a logical address for the data. The memory system may set a bit of a bitmap, which may indicate that the block includes data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any quantity of portions, each corresponding to a different subset of a logical-to-physical (L2P) table, and the bitmap may include any quantity of corresponding bits. To perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table to evaluate to determine whether different sets of data within the block are valid or invalid.

公开(公告)号：US20240369416A1

公开(公告)日：2024-11-07

申请号：US18646587

申请日：2024-04-25

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G01K1/022 ,  G01K1/02 ,  G05B19/042 ,  G06F16/2455

Abstract: Methods, systems, and devices for temperature exception tracking in a temperature log for a memory system are described. The memory system may store the temperature log separate from data to which the temperature information corresponds. For example, a memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.

公开(公告)号：US12130747B2

公开(公告)日：2024-10-29

申请号：US18081468

申请日：2022-12-14

Applicant: Micron Technology, Inc.

Inventor： Sharath Chandra Ambula ,  David Aaron Palmer ,  Venkata Kiran Kumar Matturi ,  Sri Ramya Pinisetty ,  Sushil Kumar

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/657

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

公开(公告)号：US20240289052A1

公开(公告)日：2024-08-29

申请号：US18442936

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  David Aaron Palmer ,  Reshmi Basu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0683

Abstract: Methods, systems, and devices for ordering entries of an input command queue are described. A memory system may include an interface (e.g., a host interface) that includes a queue (e.g., an input command queue). The host interface may receive commands from a host system, and the commands may be inserted into the input command queue in an order they are received. In some examples, the memory system may determine a range of logical block addresses (LBAs) associated with one or more entries in the input command queue. The memory system may order (e.g., reorder) the commands such that the respective LBA ranges are contiguous.