公开(公告)号：US20230118893A1

公开(公告)日：2023-04-20

申请号：US18084149

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F1/3225

Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.

公开(公告)号：US11574687B2

公开(公告)日：2023-02-07

申请号：US17514858

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Fuad Badrieh ,  Thomas H. Kinsley

IPC: G11C5/14 ,  G11C16/30 ,  G06F1/28 ,  G06F1/3296

Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

公开(公告)号：US20220358988A1

公开(公告)日：2022-11-10

申请号：US17315711

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/4074 ,  G11C11/22

Abstract: Methods, systems, and devices for voltage adjustment of memory dies based on weighted feedback are described. A supply voltage may be measured at various areas of a memory die, weights may be applied to the measured voltages based on the area from which the particular voltage was measured. The supply voltage may be adjusted based on the weighted signals. The signals may be weighted using digital or analog techniques. Different durations of time in which oscillations from an oscillator circuit are counted may provide weighting for a signal. Weights applied to the signals may be dynamically adjusted, which may allow the weights to be tuned or changed based on changes to operating conditions of the memory dies.

公开(公告)号：US20220303111A1

公开(公告)日：2022-09-22

申请号：US17204681

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Won Joo Yun ,  Baekkyu Choi

IPC: H04L7/02

Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

公开(公告)号：US20220076729A1

公开(公告)日：2022-03-10

申请号：US17480685

申请日：2021-09-21

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Thomas H. Kinsley ,  Fuad Badrieh

IPC: G11C11/4074 ,  G06F3/06

Abstract: Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

公开(公告)号：US20220068347A1

公开(公告)日：2022-03-03

申请号：US17470743

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/4074

Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

公开(公告)号：US11133053B2

公开(公告)日：2021-09-28

申请号：US16863967

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C5/14 ,  G11C11/4074

Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

公开(公告)号：US11133052B2

公开(公告)日：2021-09-28

申请号：US16740281

申请日：2020-01-10

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Thomas H. Kinsley ,  Fuad Badrieh

IPC: G11C11/4074 ,  G06F3/06

Abstract: Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

公开(公告)号：US10957417B2

公开(公告)日：2021-03-23

申请号：US16786748

申请日：2020-02-10

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C29/54 ,  G11C29/50 ,  G06F30/367 ,  G06F115/12 ,  G06F119/06

Abstract: Systems, apparatuses, and methods for on-die memory power analytics and management are described. In some examples, the memory analytics and management may include a frequency-dependent analysis or simulation model of a memory die to determine an operating characteristic of the die. A set of ports of the memory die may be selected and one or more alternating current (AC) excitation signals may be applied to the ports to determine an impedance associated with the ports. The impedance may be used to determine one or more parameters (e.g., scattering, impedance) to analyze a die and for subsequently managing power distribution on the die. Analytics on a subset of ports on a die may be used to simulate the electrical response of the entire memory die and thus manage power delivery for the die.

公开(公告)号：US20210074335A1

公开(公告)日：2021-03-11

申请号：US17025628

申请日：2020-09-18

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C5/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F13/16

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.