公开(公告)号：US20220301610A1

公开(公告)日：2022-09-22

申请号：US17204063

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Takamasa Suzuki ,  Yasuo Satoh ,  Yuan He ,  Hyunui Lee

IPC: G11C8/08 ,  G11C5/14 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.

公开(公告)号：US11145383B1

公开(公告)日：2021-10-12

申请号：US16848093

申请日：2020-04-14

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee

IPC: G11C7/04 ,  G11C29/12 ,  G11C29/02 ,  G11C7/10 ,  G11C29/56

Abstract: Semiconductor devices are disclosed. A semiconductor device may include an input/output (I/O) interface area. The semiconductor device may also include a number of ZQ calibration circuits, wherein each of the number of ZQ calibration circuits is positioned adjacent to an associated portion of the I/O interface area. The semiconductor device may also include a number of interpolation circuits, wherein each of the number of interpolation circuits positioned adjacent to an associated portion of the I/O interface area and configured to generate a calibration code based on a number of other calibration codes. Further, portions of the I/O interface area associated with the number of interpolation circuits are at least partially positioned between portions of the I/O interface area associated with the number of ZQ calibration circuits. Methods and systems are also disclosed.

公开(公告)号：US11677537B2

公开(公告)日：2023-06-13

申请号：US17204681

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Won Joo Yun ,  Baekkyu Choi

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40 ,  H04L7/02

CPC classification number: H04L7/02

Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

公开(公告)号：US20230025173A1

公开(公告)日：2023-01-26

申请号：US17385412

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Won Joo Yun

IPC: G06F1/10 ,  G06F1/12 ,  G06F1/08

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

公开(公告)号：US11494198B2

公开(公告)日：2022-11-08

申请号：US17141031

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee

IPC: G06F9/445 ,  G11C11/4093 ,  G11C7/10 ,  G06F3/06 ,  G06F13/20 ,  G06F1/10

Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

公开(公告)号：US20220343996A1

公开(公告)日：2022-10-27

申请号：US17238561

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Masayoshi Yamazaki

IPC: G11C29/50 ,  G11C7/10 ,  H03K19/00

Abstract: A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration code may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.

公开(公告)号：US11922996B2

公开(公告)日：2024-03-05

申请号：US17449861

申请日：2021-10-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyunui Lee ,  Won Joo Yun

IPC: G11C11/4093 ,  G11C11/4076 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  H01L25/18

Abstract: A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.

公开(公告)号：US11670397B2

公开(公告)日：2023-06-06

申请号：US17238561

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Masayoshi Yamazaki

IPC: G11C29/50 ,  G11C7/10 ,  H03K19/00

CPC classification number: G11C29/50008 ,  G11C7/109 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1096 ,  H03K19/0005 ,  G11C2207/2254

Abstract: A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration circuit may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.

公开(公告)号：US20230029528A1

公开(公告)日：2023-02-02

申请号：US17385340

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Chikara Kondo ,  Yuan He ,  Hyunui Lee

IPC: G11C29/12 ,  G11C7/22

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a data signal according to a clock signal to obtain a data sample; sampling the data signal according to an advanced clock signal to obtain an advanced data sample; and sampling the data signal according to a delayed clock signal to obtain a delayed data sample. The method may also include comparing the data sample with the advanced data sample and the delayed data sample and performing an action based on the comparison. The action may include selecting a data sample, selecting a clock signal and/or adjusting a clock signal. Associated devices and systems are also disclosed.

公开(公告)号：US20220303111A1

公开(公告)日：2022-09-22

申请号：US17204681

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Won Joo Yun ,  Baekkyu Choi

IPC: H04L7/02

Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.