公开(公告)号：US20190206870A1

公开(公告)日：2019-07-04

申请号：US15898086

申请日：2018-02-15

Applicant: Micron Technology, Inc.

Inventor： Yunfei Gao ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Haitao Liu ,  Deepak Chandra Pandey ,  Srinivas Pulugurtha ,  Kamal M. Karda

IPC: H01L27/108 ,  H01L29/20 ,  H01L29/423

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.

公开(公告)号：US20190172520A1

公开(公告)日：2019-06-06

申请号：US16250919

申请日：2019-01-17

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Chandra Mouli ,  Haitao Liu

IPC: G11C11/408 ,  G11C8/08 ,  G11C8/14 ,  H01L23/532 ,  H01L23/528 ,  H01L27/108

Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.

公开(公告)号：US20180374531A1

公开(公告)日：2018-12-27

申请号：US15633595

申请日：2017-06-26

Applicant: Micron Technology, Inc

Inventor： Deepak Chandra Pandey ,  Chandra Mouli ,  Haitao Liu

IPC: G11C11/408 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.

公开(公告)号：US11910597B2

公开(公告)日：2024-02-20

申请号：US17734410

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H10B41/27 ,  G11C5/06 ,  G11C5/02 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11769795B2

公开(公告)日：2023-09-26

申请号：US17499410

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L21/762 ,  H10B12/00

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H10B12/053 ,  H10B12/31 ,  H10B12/34

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US11569353B2

公开(公告)日：2023-01-31

申请号：US17165753

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Venkata Naveen Kumar Neelapala ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/165

Abstract: An apparatus comprises active word lines extending within a semiconductive material, passing word lines extending adjacent to the active word lines within the semiconductive material, isolation regions adjacent to the passing word lines, and a band offset material adjacent to the passing word lines and the isolation regions. The semiconductive material exhibits a first bandgap and the band offset material exhibits a second, different bandgap. Related methods and systems are also described.

公开(公告)号：US11538809B2

公开(公告)日：2022-12-27

申请号：US17007327

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Litao Yang ,  Srinivas Pulugurtha ,  Yunfei Gao ,  Haitao Liu

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L49/02 ,  H01L21/02

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.

公开(公告)号：US20220301941A1

公开(公告)日：2022-09-22

申请号：US17824744

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11507 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/792 ,  H01L27/24 ,  H01L21/8239 ,  H01L27/108

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

公开(公告)号：US20210183865A1

公开(公告)日：2021-06-17

申请号：US16711531

申请日：2019-12-12

Applicant: Micron Technology, Inc.

Inventor： Venkata Naveen Kumar Neelapala ,  Deepak Chandra Pandey ,  Naveen Kaushik

IPC: H01L27/108

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.

公开(公告)号：US10825816B2

公开(公告)日：2020-11-03

申请号：US15898086

申请日：2018-02-15

Applicant: Micron Technology, Inc.

Inventor： Yunfei Gao ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Haitao Liu ,  Deepak Chandra Pandey ,  Srinivas Pulugurtha ,  Kamal M. Karda

IPC: H01L23/58 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L27/108 ,  H01L29/423 ,  H01L29/20 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L29/267

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.