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公开(公告)号：US11328779B2
公开(公告)日：2022-05-10
申请号：US17097447
申请日：2020-11-13
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Dustin J. Carter
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
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公开(公告)号：US20210173771A1
公开(公告)日：2021-06-10
申请号：US16709380
申请日：2019-12-10
Applicant: Micron Technology, Inc.
Inventor： Suresh Rajgopal , Jeremy W. Butterfield , Sean E. Nerich , Dustin J. Carter
IPC: G06F12/02 , G06F12/0831 , G06F12/0868 , G06F12/0882 , G06F9/54
Abstract: A read command to read a target memory die of a memory sub-system is received from a host system via a host-side interface of an active input/output (I/O) expander. The active I/O expander identifies a page address corresponding to the target memory die and decodes the read command to send to a memory stack associated with the page address corresponding to the target memory die. Read data is received via a memory-side interface of the active I/O expander from the memory stack including the target memory die. A signal conditioning operation is performed on the read data to generate conditioned read data. The active I/O expander sends, via the host-side interface, the conditioned read data to the host system.
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公开(公告)号：US10956576B2
公开(公告)日：2021-03-23
申请号：US16123084
申请日：2018-09-06
Applicant: Micron Technology, Inc.
Inventor： Robert W. Strong , Dustin J. Carter , Neil Levine
Abstract: A variety of applications can include apparatus and/or methods of controlling a secure boot mode for a memory system. In an embodiment, a system includes a memory component and a processing device, where the processing device is configured to control a boot process for the system to operate the memory component and perform a cryptographic verification with a host to conduct an authentication of the host. The processing device can interact with the host, in response to the authentication, to receive a setting to control the boot process in a secure boot mode. The processing can interact with another processing device of the system to store the setting and to receive a secure boot signal from the other processing device, where the secure boot signal is a signal to assert or de-assert the secure boot mode depending on a value of the setting. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20200082089A1
公开(公告)日：2020-03-12
申请号：US16123084
申请日：2018-09-06
Applicant: Micron Technology, Inc.
Inventor： Robert W. Strong , Dustin J. Carter , Neil Levine
Abstract: A variety of applications can include apparatus and/or methods of controlling a secure boot mode for a memory system. In an embodiment, a system includes a memory component and a processing device, where the processing device is configured to control a boot process for the system to operate the memory component and perform a cryptographic verification with a host to conduct an authentication of the host. The processing device can interact with the host, in response to the authentication, to receive a setting to control the boot process in a secure boot mode. The processing can interact with another processing device of the system to store the setting and to receive a secure boot signal from the other processing device, where the secure boot signal is a signal to assert or de-assert the secure boot mode depending on a value of the setting. Additional apparatus, systems, and methods are disclosed.
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