公开(公告)号：US11514969B2

公开(公告)日：2022-11-29

申请号：US17381996

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Ferdinando Bedeschi ,  Suryanarayana B. Tatapudi ,  Hyunyoo Lee ,  Adam S. El-Mansouri

IPC: G11C11/22

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

公开(公告)号：US11475937B2

公开(公告)日：2022-10-18

申请号：US17338458

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira S. Malik ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G11C11/4074 ,  H01L25/065 ,  H01L27/108 ,  H02M3/156

Abstract: Methods, systems, and devices for die voltage regulation are described. A device may include a first die and second die. A component that generates voltage on the first die may be connected to a capacitor on the second die through a conductive line. The conductive line may allow the capacitor on the second die to regulate voltage generated by the component on the first die.

公开(公告)号：US20220020415A1

公开(公告)日：2022-01-20

申请号：US17381996

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Ferdinando Bedeschi ,  Suryanarayana B. Tatapudi ,  Hyunyoo Lee ,  Adam S. El-Mansouri

IPC: G11C11/22

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

公开(公告)号：US12176059B2

公开(公告)日：2024-12-24

申请号：US18407062

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyunyoo Lee

IPC: G11C7/10

Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

公开(公告)号：US20240347123A1

公开(公告)日：2024-10-17

申请号：US18647867

申请日：2024-06-07

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Kang-Yong Kim

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/4401

Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

公开(公告)号：US20240302998A1

公开(公告)日：2024-09-12

申请号：US18608591

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0602 ,  G06F3/0673

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

公开(公告)号：US20230121992A1

公开(公告)日：2023-04-20

申请号：US17502792

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyunyoo Lee

IPC: G11C7/10

Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

公开(公告)号：US20230100397A1

公开(公告)日：2023-03-30

申请号：US17959730

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira S. Malik ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G11C11/4074 ,  H01L25/065 ,  H02M3/156 ,  H01L27/108

Abstract: Methods, systems, and devices for die voltage regulation are described. A device may include a first die and second die. A component that generates voltage on the first die may be connected to a capacitor on the second die through a conductive line. The conductive line may allow the capacitor on the second die to regulate voltage generated by the component on the first die.

公开(公告)号：US20220406344A1

公开(公告)日：2022-12-22

申请号：US17648403

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Taeksang Song

IPC: G11C7/10 ,  G11C8/06 ,  G11C11/4074

Abstract: Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

公开(公告)号：US20210398601A1

公开(公告)日：2021-12-23

申请号：US17349612

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Hyunyoo Lee ,  Saira Samar Malik ,  Kang-Yong Kim

IPC: G11C29/10 ,  G11C29/36 ,  G11C29/12 ,  G11C29/14 ,  G11C29/18

Abstract: Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.