Data storage device identifying tenants and operating method thereof

    公开(公告)号:US11995313B2

    公开(公告)日:2024-05-28

    申请号:US17938011

    申请日:2022-10-04

    IPC分类号: G06F3/06

    摘要: A data storage device includes a volatile memory device including a first table area storing a first table having a plurality of first unit information, and a nonvolatile memory device including a subtree area and a second table area. The second table area stores sorted string tables (SSTables) of level 0 each including a respective plurality of first unit information. Each first unit information includes a key corresponding to a key-value (KV) command and a namespace identifying a tenant providing that KV command. The second table area and the subtree area form a data structure which can be queried with a key included in a KV command. The subtree area includes a plurality of subtrees respectively corresponding to a plurality of namespaces, each subtree storing an SSTable of level 1 having a plurality of second unit information each having a key related to the corresponding namespace of that subtree.

    Memory system and operating method thereof

    公开(公告)号:US11726878B2

    公开(公告)日:2023-08-15

    申请号:US17191190

    申请日:2021-03-03

    申请人: SK hynix Inc.

    发明人: Kwang Su Kim

    IPC分类号: G06F11/14 G06F3/06

    摘要: Embodiments of the present disclosure relate to a memory system and an operating method thereof. The memory system may include a first processor and a second processor. The first processor is configured to manage or process a main read count table including a plurality of first read count table entries each corresponding to one of a plurality of super memory blocks. The second processor is configured to manage or process, when an error occurs during an operation of reading data stored in one of the plurality of super memory blocks, a partial read count table including a read count table entry including information on a count of the read operation executed during a recovery operation for the error, and transmit an update message to the first processor for updating the main read count table based on the partial read count table.

    Storage Isolation for Containers
    5.
    发明申请

    公开(公告)号:US20180129821A1

    公开(公告)日:2018-05-10

    申请号:US15628089

    申请日:2017-06-20

    IPC分类号: G06F21/62 G06F3/06

    摘要: An application running in a container is able to access files stored on disk via normal file system calls, but in a manner that remains isolated from applications and processes in other containers. In one aspect, a namespace virtualization component is coupled with a copy-on-write component. When an isolated application is accessing a file stored on disk in a read-only manner, the namespace virtualization component and copy-on-write component grant access to the file. But, if the application requests to modify the file, the copy-on-write component intercepts the I/O and effectively creates a copy of the file in a different storage location on disk. The namespace virtualization component is then responsible for hiding the true location of the copy of the file, via namespace mapping.

    AFFINITY-AWARE PARALLEL ZEROING OF PAGES IN NON-UNIFORM MEMORY ACCESS (NUMA) SERVERS
    7.
    发明申请
    AFFINITY-AWARE PARALLEL ZEROING OF PAGES IN NON-UNIFORM MEMORY ACCESS (NUMA) SERVERS 有权
    非均匀存储器访问(NUMA)服务器中的AFFINITY-AWARE并行调整页

    公开(公告)号:US20160378397A1

    公开(公告)日:2016-12-29

    申请号:US14883361

    申请日:2015-10-14

    IPC分类号: G06F3/06

    摘要: Embodiments disclosed herein generally relate to techniques for zeroing memory in computing systems where access to memory is non-uniform. One embodiment provides a processor which performs an operation including receiving, via a system call, a request to delete a memory region. The operation also includes sorting, after receiving the request, one or more pages of the memory region according to each of the one or more pages associated affinity domain. The operation further includes sending requests to zero the sorted one or more pages to one or more zeroing threads that are attached to the respective affinity domain. The operation further yet includes waiting, after sending the requests, to return to the system caller until a message is received, from the worker threads in each affinity domain, indicating that all the page zeroing requests have been processed.

    摘要翻译: 本文公开的实施例通常涉及用于对存储器访问不均匀的计算系统中的存储器归零的技术。 一个实施例提供一种执行操作的处理器,包括经由系统调用接收删除存储器区域的请求。 所述操作还包括在接收到所述请求之后,根据所述一个或多个页面相关联的关联域中的每一个来排序所述存储器区域的一个或多个页面。 该操作还包括发送请求,将排序的一个或多个页面归零到附接到相应的亲和域的一个或多个归零线程。 操作进一步包括在发送请求之后,等待来自系统调用者的信息,直到接收到消息,从每个关联域中的工作线程,指示所有的页面归零请求已被处理。

    Distributing media using a portable digital device compatible with optical drive devices
    8.
    发明授权
    Distributing media using a portable digital device compatible with optical drive devices 有权
    使用与光驱设备兼容的便携式数字设备分发媒体

    公开(公告)号:US09159370B2

    公开(公告)日:2015-10-13

    申请号:US11699804

    申请日:2007-01-29

    摘要: A media distribution system is provided in which a primary means of transport for digital media is through a device with housing shaped as an optical disc and insertable into various current and future optical disc drive devices. Media travels from different digital sources such as a personal media library and other networked resources to embedded memory on the optical disc shaped device via a capable personal computer or electronic device. This media is then able to be presented in the most appropriate format in a number of different types of current and legacy devices with optical drives such as CD audio devices and DVD players.

    摘要翻译: 提供了一种媒体分发系统,其中用于数字媒体的主要传送装置通过具有被形成为光盘并且可插入到各种当前和将来的光盘驱动装置中的壳体的装置。 媒体可以通过有能力的个人计算机或电子设备从诸如个人媒体库和其他网络资源的不同数字源传播到光盘形设备上的嵌入式存储器。 然后,能够以多种不同类型的具有诸如CD音频设备和DVD播放器之类的光驱的当前和旧设备呈现最适当的格式的媒体。

    FAST AND FLEXIBLE RAM READER AND WRITER
    10.
    发明公开

    公开(公告)号:US20230376229A1

    公开(公告)日:2023-11-23

    申请号:US17663847

    申请日:2022-05-18

    发明人: Walter Girardi

    IPC分类号: G06F3/06

    摘要: A circuit for reading or writing a RAM includes a shift register coupled to the RAM, a test data input, and a test data output. The circuit further includes a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.