公开(公告)号：US20190148358A1

公开(公告)日：2019-05-16

申请号：US16007903

申请日：2018-06-13

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  John B. Pusey ,  Zhiping Yin ,  Kevin G. Duesman

IPC: H01L27/02 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L49/02 ,  H01L27/115

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

公开(公告)号：US10128229B1

公开(公告)日：2018-11-13

申请号：US15811572

申请日：2017-11-13

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  John B. Pusey ,  Zhiping Yin ,  Kevin G. Duesman

IPC: H01L27/02 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L49/02 ,  H01L27/115

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

公开(公告)号：US20240395325A1

公开(公告)日：2024-11-28

申请号：US18647354

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  James E. Davis ,  Kenneth W. Marr

IPC: G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B99/00

Abstract: A semiconductor device including a substrate; a substrate; a memory array disposed on the substrate, the memory array including one or more memory planes, and a plurality of source region contact (SRC) nodes that are disposed on a backside surface of corresponding one of the one or more memory planes and above the substrate; a plurality of high-voltage (HV) diodes that are disposed in the substrate and that are connected to corresponding SRC nodes, the HV diodes including a first type dopant material; and a plurality of highly doped regions that are disposed in the substrate and that include a second type dopant material, each of the plurality of highly doped regions including a plurality of local maximum doping regions that are vertically aligned under a frontside surface of the substrate.

公开(公告)号：US20240372360A1

公开(公告)日：2024-11-07

申请号：US18647962

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  Michael D. Chaine ,  Gregory A. King ,  Liuchun Cai

IPC: H02H9/04 ,  G11C5/14

Abstract: An apparatus includes a first voltage domain including a first circuit configured to operate at a first supply voltage, a second voltage domain including second circuit configured to operate at a second supply voltage, and a drain-ballasted electrostatic discharge (ESD) protection circuit configured to electrically couple the first voltage domain and the second voltage domain, the drain-ballasted ESD protection circuit including a first NMOS transistor, a second NMOS transistor, a floating interconnect that electrically couples the first NMOS transistor to the second NMOS transistor, and a grounding resistor coupled to the first NMOS transistor and the second NMOS transistor.

公开(公告)号：US20240071516A1

公开(公告)日：2024-02-29

申请号：US17897448

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth W. Marr ,  James E. Davis ,  Chiara Cerafogli

IPC: G11C16/22 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/22 ,  G11C16/0483 ,  G11C16/16

Abstract: A discharge circuit includes a transistor and a metal resistor connected to the transistor. The transistor includes a plurality of unit cells. The metal resistor includes a plurality of resistor portions corresponding to the plurality of unit cells. Each unit cell of the plurality of unit cells has a footprint and a corresponding resistor portion of the plurality of resistor portions is arranged within the footprint.

公开(公告)号：US11798935B2

公开(公告)日：2023-10-24

申请号：US17871681

申请日：2022-07-22

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  Milind Nemchand Furia ,  Michael D. Chaine ,  Eric J. Smith

IPC: G11C16/30 ,  G11C16/04 ,  G11C5/14 ,  H01L27/02 ,  H01L21/8222

CPC classification number: H01L27/0262 ,  G11C5/14 ,  G11C16/30 ,  H01L21/8222 ,  G11C16/0483

Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

公开(公告)号：US11508657B2

公开(公告)日：2022-11-22

申请号：US16990886

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  Kevin G. Duesman

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66 ,  H01L23/62 ,  H01L49/02 ,  H01L23/64 ,  H01L27/11578 ,  H01L27/11551

Abstract: Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component.

公开(公告)号：US20220199554A1

公开(公告)日：2022-06-23

申请号：US17176787

申请日：2021-02-16

Applicant: Micron Technology, Inc.

Inventor： Yui Shimizu ,  James E. Davis

IPC: H01L23/60 ,  H01L25/065 ,  H01L25/00

Abstract: A memory device including a substrate including a substrate contact pad. The memory device includes a first memory die including a first power supply contact pad electrically coupled to the substrate contact pad and a first power supply circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power supply contact pad electrically coupled to the substrate contact pad and a second power supply circuit on the second memory die and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact.

公开(公告)号：US11056467B2

公开(公告)日：2021-07-06

申请号：US16590595

申请日：2019-10-02

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Duesman ,  James E. Davis ,  Warren L. Boyer

IPC: H01L25/065 ,  H01L23/00 ,  H01L27/02 ,  H01L25/00 ,  H01L23/498 ,  H01L23/60 ,  H01L23/48 ,  H01L23/538 ,  H01L23/482

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

公开(公告)号：US10811372B2

公开(公告)日：2020-10-20

申请号：US16416210

申请日：2019-05-18

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  Kevin G. Duesman ,  Jeffrey P. Wright ,  Warren L. Boyer

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/538 ,  H01L25/04 ,  G11C5/02 ,  H01L25/065

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.