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    Power Management Integrated Circuit Load Switch Driver with Dynamic Biasing
    21.
    发明申请
    Power Management Integrated Circuit Load Switch Driver with Dynamic Biasing 审中-公开

    公开(公告)号：US20190279688A1

    公开(公告)日：2019-09-12

    申请号：US15919020

    申请日：2018-03-12

    Applicant: Micron Technology, Inc.

    Inventor： Matthew David Rowley

    IPC: G11C5/14 ,  H03K17/687 ,  G06F1/28 ,  G06F1/30

    Abstract: Disclosed is an improved load switch driver for power management integrated circuit (PMIC) devices. In one embodiment, a PMIC is disclosed comprising a gate driver, the gate driver connected to the gate of a switch; an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and a voltage sensor, the voltage sensor connected to the operation frequency generator and the source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower the frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.

    Power management integrated circuit with dual power feed
    24.
    发明授权
    Power management integrated circuit with dual power feed 有权

    公开(公告)号：US11514955B2

    公开(公告)日：2022-11-29

    申请号：US17018051

    申请日：2020-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Matthew David Rowley

    IPC: G11C16/04 ,  G11C5/14 ,  G06F1/26 ,  G06F1/28

    Abstract: A power management circuit receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the circuit generates an interrupt signal causing the memory system to shut down safely without data loss.

    Low power state implementation in a power management circuit
    25.
    发明授权
    Low power state implementation in a power management circuit 有权

    公开(公告)号：US11243602B2

    公开(公告)日：2022-02-08

    申请号：US16554896

    申请日：2019-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Matthew David Rowley

    IPC: G06F1/3296 ,  G11C16/26 ,  G06F12/02 ,  H01L27/11526 ,  G11C7/20 ,  G11C7/22 ,  H01L27/11521 ,  G11C16/30 ,  G11C5/14 ,  G11C7/10 ,  G06F1/3234

    Abstract: A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

    HARDWARE-BASED POWER MANAGEMENT INTEGRATED CIRCUIT REGISTER FILE WRITE PROTECTION
    26.
    发明申请
    HARDWARE-BASED POWER MANAGEMENT INTEGRATED CIRCUIT REGISTER FILE WRITE PROTECTION 有权

    公开(公告)号：US20210026569A1

    公开(公告)日：2021-01-28

    申请号：US17066305

    申请日：2020-10-08

    Applicant: Micron Technology, Inc.

    Inventor： Matthew David Rowley

    IPC: G06F3/06 ,  G11C5/14

    Abstract: Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

    Hardware-based power management integrated circuit register file write protection
    27.
    发明授权
    Hardware-based power management integrated circuit register file write protection 有权

    公开(公告)号：US10802754B2

    公开(公告)日：2020-10-13

    申请号：US15919026

    申请日：2018-03-12

    Applicant: Micron Technology, Inc.

    Inventor： Matthew David Rowley

    IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C5/14

    Abstract: Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

    Power management integrated circuit load switch driver with dynamic biasing
    28.
    发明授权
    Power management integrated circuit load switch driver with dynamic biasing 有权

    公开(公告)号：US10755750B2

    公开(公告)日：2020-08-25

    申请号：US16661904

    申请日：2019-10-23

    Applicant: Micron Technology, Inc.

    Inventor： Matthew David Rowley

    IPC: G11C5/14 ,  G11C11/4074 ,  G06F1/28 ,  G06F1/30 ,  H03K17/687

    Abstract: Disclosed is an improved load switch driver for Power Management Integrated Circuit (PMIC) devices. In one embodiment, a PMIC is disclosed comprising a gate driver, the gate driver connected to the gate of a switch; an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and a voltage sensor, the voltage sensor connected to the operation frequency generator and the source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower the frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.

    Low Power State Implementation in a Power Management Circuit
    29.
    发明申请
    Low Power State Implementation in a Power Management Circuit 审中-公开

    公开(公告)号：US20190384377A1

    公开(公告)日：2019-12-19

    申请号：US16554896

    申请日：2019-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Matthew David Rowley

    IPC: G06F1/3296 ,  G11C7/20 ,  G11C16/30 ,  H01L27/11521 ,  G11C16/26 ,  H01L27/11526 ,  G06F12/02 ,  G11C7/22

    Abstract: A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

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