公开(公告)号：US20220113970A1

公开(公告)日：2022-04-14

申请号：US17558140

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Nadav Grosz

IPC: G06F9/30 ,  G06F3/06 ,  G06F9/48 ,  G06F12/1009

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

公开(公告)号：US20210263864A1

公开(公告)日：2021-08-26

申请号：US16801949

申请日：2020-02-26

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna ,  Nadav Grosz

IPC: G06F12/14 ,  G06F12/02 ,  G06F12/06 ,  G06F1/24 ,  G06F21/79

Abstract: An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.

公开(公告)号：US20210073121A1

公开(公告)日：2021-03-11

申请号：US16565066

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A a current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.

公开(公告)号：US20210056044A1

公开(公告)日：2021-02-25

申请号：US16544337

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  Jonathan Scott Parry

IPC: G06F12/14 ,  G06F12/02 ,  G06F21/78

Abstract: Devices and techniques for efficient host assisted logical-to-physical (L2P) mapping are described herein. For example, a command can be executed that results in a change as to which physical address of a memory device corresponds to a logical address. The change can be obfuscated as part of an obfuscated L2P map for the memory device and written to storage on the memory device. The change can then be provided a host from the storage.

公开(公告)号：US10884659B2

公开(公告)日：2021-01-05

申请号：US16023177

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A timer of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.

公开(公告)号：US20200210279A1

公开(公告)日：2020-07-02

申请号：US16237263

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Jonathan Parry ,  Nadav Grosz ,  David Aaron Palmer ,  Christian M. Gyllenskog

IPC: G06F11/10 ,  G06F12/02 ,  G06F3/06

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

公开(公告)号：US20200097194A1

公开(公告)日：2020-03-26

申请号：US16140952

申请日：2018-09-25

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz

IPC: G06F3/06 ,  G06F12/10

Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.

公开(公告)号：US20250117150A1

公开(公告)日：2025-04-10

申请号：US18776201

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz

IPC: G06F3/06

Abstract: Methods, systems, and devices for data transfer during maintenance operations are described. A memory system utilize an auto-suspend feature to parallelize aspects of maintenance operations. For example, the memory system may suspend a programming operation being performed on a first block of memory cells. The memory system may read data from a second block of memory cells while the programming operation is suspended, and may transfer the data from the second block of memory cells (e.g., to a controller) in parallel with resuming the programming operation on the first block of memory cells. The memory system may transfer the data read from the second block of memory cells to a third block of memory cells in parallel with resuming the programming operation on the first block of memory cells.

公开(公告)号：US12260088B2

公开(公告)日：2025-03-25

申请号：US17663722

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Marco Onorato ,  Luca Porzio ,  Roberto Izzi ,  Nadav Grosz

IPC: G06F3/06

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

公开(公告)号：US11847468B2

公开(公告)日：2023-12-19

申请号：US17645687

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Luca Porzio ,  Roberto Izzi ,  Francesco Falanga ,  Nadav Grosz ,  Massimo Iaculo

IPC: G06F9/4401 ,  G06F3/06

CPC classification number: G06F9/4406 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0683

Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.