Accessing memory devices via switchable channels

    公开(公告)号:US12189958B2

    公开(公告)日:2025-01-07

    申请号:US17898160

    申请日:2022-08-29

    Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.

    SECOND READ INITIALIZATION ON LATCH-LIMITED MEMORY DEVICE

    公开(公告)号:US20240361929A1

    公开(公告)日:2024-10-31

    申请号:US18768806

    申请日:2024-07-10

    Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.

Patent Agency Ranking