公开(公告)号：US12061806B2

公开(公告)日：2024-08-13

申请号：US17858778

申请日：2022-07-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.

公开(公告)号：US20240134571A1

公开(公告)日：2024-04-25

申请号：US18401251

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sivagnanam Parthasarathy ,  Patrick R. Khayat ,  Sundararajan Sankaranarayanan ,  Jeremy Binfet ,  Akira Goda

IPC: G06F3/06 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G11C16/26 ,  G11C16/0483

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.

公开(公告)号：US20240069738A1

公开(公告)日：2024-02-29

申请号：US17898160

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan ,  Xiangyu Tang ,  Dustin J. Carter

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0679

Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.

公开(公告)号：US20240069721A1

公开(公告)日：2024-02-29

申请号：US17823909

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Sundararajan Sankaranarayanan ,  Chulbum Kim ,  Xiangyu Tang

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0679

Abstract: Memory with switchable channels is disclosed herein. In one embodiment, a system comprises a controller, a plurality of memory dies, and a switch matrix. The switch matrix is coupled to the controller via two or more controller-side channels, and to the plurality of memory dies via a set of memory-side channels. The switch matrix is configured to selectively couple each controller-side channel of the two or more controller-side channels to each memory-side channel of the set of memory-side channels to provide dynamically configurable connections between the controller and one or more memory dies of the plurality of memory dies.

公开(公告)号：US20230393976A1

公开(公告)日：2023-12-07

申请号：US17830047

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Tang ,  David Ebsen ,  Ying Huang ,  Sundararajan Sankaranarayanan

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0253 ,  G06F3/0652 ,  G06F3/0604 ,  G06F3/0679

Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.

公开(公告)号：US11687237B2

公开(公告)日：2023-06-27

申请号：US17393727

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.

公开(公告)号：US20230148018A1

公开(公告)日：2023-05-11

申请号：US18095646

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Sundararajan Sankaranarayanan ,  Eric Nien-Heng Lee ,  Akira Goda

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C11/4085 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C16/34 ,  G11C16/26 ,  G11C2211/5642 ,  G11C16/0483

Abstract: A device includes an array of memory cells with a first word line coupled to at least a subset of the array of memory cells and control logic coupled to the first word line. The control logic to detect, within a queue, a first read command to read first data from a first page of the subset and a second read command to read second data from a second page of the subset. The control logic is further to cause a voltage applied to the first word line to move to a target value. The control logic is further to cause a page buffer to sense the first data from a first bit line coupled to the first page and to sense the second data from a second bit line coupled to the second page. The control logic is further to cause the first word line to be discharged.

公开(公告)号：US20250077086A1

公开(公告)日：2025-03-06

申请号：US18950798

申请日：2024-11-18

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan ,  Xiangyu Tang ,  Dustin J. Carter

IPC: G06F3/06

Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, wherein the memory sub-system controller provides a plurality of channel mappings, wherein a first channel mapping of the plurality of channel mappings identifies a first controller channel of the plurality of controller channels and one or more first memory channels of a plurality of memory channels, and wherein a second channel mapping of the plurality of channel mappings identifies a second controller channel of the plurality of controller channels and one or more second memory channels of the plurality of memory channels; one or more memory devices comprising the plurality of memory channels, wherein the one or more memory devices comprise a plurality of memory dies, wherein each memory channel of the plurality of memory channels corresponds to a respective one of the plurality of memory dies; and a channel switch circuit coupled between the plurality of the controller channels and the plurality of memory channels, wherein each controller channel of the plurality of the controller channels is capable to be mapped to the plurality of memory channels for data routing.

公开(公告)号：US20240202114A1

公开(公告)日：2024-06-20

申请号：US18591777

申请日：2024-02-29

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Tang ,  David Ebsen ,  Ying Huang ,  Sundararajan Sankaranarayanan

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0253 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.

公开(公告)号：US20230045463A1

公开(公告)日：2023-02-09

申请号：US17393727

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan

IPC: G06F3/06

Abstract: A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.