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公开(公告)号：US20230214299A1
公开(公告)日：2023-07-06
申请号：US17566921
申请日：2021-12-31
Applicant: Micron Technology, Inc.
Inventor： Priya Venkataraman , Pitamber Shukla , Vipul Patel , Scott A. Stoller
IPC: G06F11/10 , G06F11/07 , G06F12/0882 , G06F3/06
CPC classification number: G06F11/108 , G06F11/0772 , G06F11/0793 , G06F12/0882 , G06F3/0656 , G06F3/0619 , G06F3/0688
Abstract: Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.
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公开(公告)号：US20210405723A1
公开(公告)日：2021-12-30
申请号：US17472862
申请日：2021-09-13
Applicant: Micron Technology, Inc.
Inventor： Vipul Patel
IPC: G06F1/28 , G06F1/3296 , G06F3/06 , G06F1/3206 , G06F1/3234
Abstract: The present disclosure includes apparatuses and methods for providing indications associated with power management events. An example apparatus may include a plurality of memory units coupled to a shared power management signal. In this example apparatus, each of the plurality of memory units may be configured to provide to the other of the plurality of memory units, via the shared power management signal, an indication of whether the one of the plurality of memory units is entering a power management event. Further, each of the plurality of memory units may be configured to, if the one of the plurality of memory units is entering the power management event, an indication of a particular operation type associated with the power management event.
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23.发明授权公开(公告)号：US11119556B2
公开(公告)日：2021-09-14
申请号：US16550379
申请日：2019-08-26
Applicant: Micron Technology, Inc.
Inventor： Vipul Patel
IPC: G06F1/28 , G06F1/3296 , G06F3/06 , G06F1/3206 , G06F1/3234
Abstract: The present disclosure includes apparatuses and methods for providing indications associated with power management events. An example apparatus may include a plurality of memory units coupled to a shared power management signal. In this example apparatus, each of the plurality of memory units may be configured to provide to the other of the plurality of memory units, via the shared power management signal, an indication of whether the one of the plurality of memory units is entering a power management event. Further, each of the plurality of memory units may be configured to, if the one of the plurality of memory units is entering the power management event, an indication of a particular operation type associated with the power management event.
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公开(公告)号：US20210183451A1
公开(公告)日：2021-06-17
申请号：US17188153
申请日：2021-03-01
Applicant: Micron Technology, Inc.
Inventor： Vipul Patel , Theodore Pekny
Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.
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Patent Agency Ranking
25.发明申请公开(公告)号：US20210132868A1
公开(公告)日：2021-05-06
申请号：US17149790
申请日：2021-01-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vipul Patel , Theodore T. Pekny
Abstract: Memories might include an array of memory cells, a status register, and a controller for access of the array of memory cells. The controller might further be configured to perform a first read operation of a plurality of read operations in response to a read command associated with a plurality of addresses, store a first status value to the status register in response to data of the first read operation being available for readout, begin a second read operation of the plurality of read operations after completing the first read operation, and store a second value, different than the first value, to the status register in response to data of the second read operation being available for readout.
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公开(公告)号：US10937506B1
公开(公告)日：2021-03-02
申请号：US16543271
申请日：2019-08-16
Applicant: Micron Technology, Inc.
Inventor： Vipul Patel , Theodore Pekny
Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.
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公开(公告)号：US20210050063A1
公开(公告)日：2021-02-18
申请号：US16543271
申请日：2019-08-16
Applicant: Micron Technology, Inc.
Inventor： Vipul Patel , Theodore Pekny
Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.
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公开(公告)号：US20200312411A1
公开(公告)日：2020-10-01
申请号：US16903861
申请日：2020-06-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vipul Patel
Abstract: Memories including a controller configured to cause the memory to read a plurality of memory cells using a read voltage having a particular voltage level, determine a number of memory cells of a first subset of memory cells of the plurality of memory cells having a particular data state in response to the read voltage having the particular voltage level, and in response to determining that the number of memory cells of the first subset of memory cells having the particular data state is less than a particular threshold, adjust the voltage level of the read voltage based on the number of memory cells of the first subset of memory cells having the particular data state, and re-read the plurality of memory cells using the read voltage having the adjusted voltage level.
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公开(公告)号：US20190179392A1
公开(公告)日：2019-06-13
申请号：US15838048
申请日：2017-12-11
Applicant: Micron Technology, Inc.
Inventor： Vipul Patel
Abstract: The present disclosure includes apparatuses and methods for providing indications associated with power management events. An example apparatus may include a plurality of memory units coupled to a shared power management signal. In this example apparatus, each of the plurality of memory units may be configured to provide to the other of the plurality of memory units, via the shared power management signal, an indication of whether the one of the plurality of memory units is entering a power management event. Further, each of the plurality of memory units may be configured to, if the one of the plurality of memory units is entering the power management event, an indication of a particular operation type associated with the power management event.
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