公开(公告)号：US11735272B2

公开(公告)日：2023-08-22

申请号：US17572057

申请日：2022-01-10

Applicant: Micron Technology, Inc.

Inventor： Theodore Pekny

IPC: G11C16/26 ,  G06F12/0802 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F12/0802 ,  G11C16/04

Abstract: A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to detect an occurrence of a high noise event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a quiet event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the quiet event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to manage execution of the high noise event and the quiet event based on respective priorities of the first and second independent plane driver circuits.

公开(公告)号：US20220013179A1

公开(公告)日：2022-01-13

申请号：US16946867

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Theodore Pekny

IPC: G11C16/26 ,  G11C16/04 ,  G06F12/0802

Abstract: A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to track a status of the plurality of independent plane driver circuits and detect an occurrence of a quiet event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a high noise event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the high noise event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to determine whether the first independent plane driver circuit has a higher priority than the second independent plane driver circuit. Responsive to determining that the first independent plane driver circuit has a higher priority than the second independent plane driver circuit, the control logic is to suspend the high noise event associated with the second independent plane driver circuit and permitting the quiet event associated with the first independent plane driver circuit to occur.

公开(公告)号：US20220319612A1

公开(公告)日：2022-10-06

申请号：US17845785

申请日：2022-06-21

Applicant: Micron Technology, Inc.

Inventor： Vipul Patel ,  Theodore Pekny

IPC: G11C16/22 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.

公开(公告)号：US12260919B2

公开(公告)日：2025-03-25

申请号：US17845785

申请日：2022-06-21

Applicant: Micron Technology, Inc.

Inventor： Vipul Patel ,  Theodore Pekny

IPC: G11C16/22 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.

公开(公告)号：US11386964B2

公开(公告)日：2022-07-12

申请号：US17188153

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Vipul Patel ,  Theodore Pekny

IPC: G11C16/22 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.

公开(公告)号：US20220199169A1

公开(公告)日：2022-06-23

申请号：US17572057

申请日：2022-01-10

Applicant: Micron Technology, Inc.

Inventor： Theodore Pekny

IPC: G11C16/26 ,  G11C16/04 ,  G06F12/0802

Abstract: A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to detect an occurrence of a high noise event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a quiet event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the quiet event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to manage execution of the high noise event and the quiet event based on respective priorities of the first and second independent plane driver circuits.

公开(公告)号：US11222702B1

公开(公告)日：2022-01-11

申请号：US16946867

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Theodore Pekny

IPC: G11C16/00 ,  G11C16/26 ,  G06F12/0802 ,  G11C16/04

Abstract: A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to track a status of the plurality of independent plane driver circuits and detect an occurrence of a quiet event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a high noise event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the high noise event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to determine whether the first independent plane driver circuit has a higher priority than the second independent plane driver circuit. Responsive to determining that the first independent plane driver circuit has a higher priority than the second independent plane driver circuit, the control logic is to suspend the high noise event associated with the second independent plane driver circuit and permitting the quiet event associated with the first independent plane driver circuit to occur.

公开(公告)号：US20210183451A1

公开(公告)日：2021-06-17

申请号：US17188153

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Vipul Patel ,  Theodore Pekny

IPC: G11C16/22 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.

公开(公告)号：US10937506B1

公开(公告)日：2021-03-02

申请号：US16543271

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Vipul Patel ,  Theodore Pekny

IPC: G11C16/22 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/14

Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.

公开(公告)号：US20210050063A1

公开(公告)日：2021-02-18

申请号：US16543271

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Vipul Patel ,  Theodore Pekny

IPC: G11C16/22 ,  G11C16/10 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/26

Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.