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公开(公告)号：US12260486B2
公开(公告)日：2025-03-25
申请号：US17946828
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： John Burgess , Gregory Muthler , Nikhil Dixit , Henry Moreton , Yury Uralsky , Magnus Andersson , Marco Salvi , Christoph Kubisch
IPC: G06T15/50 , G06T1/60 , G06T9/00 , G06T15/00 , G06T15/06 , G06T15/40 , G06T17/10 , G06T17/20 , G06T19/20
Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.
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公开(公告)号：US12249022B2
公开(公告)日：2025-03-11
申请号：US17946515
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： John Burgess , Gregory Muthler , Nikhil Dixit , Henry Moreton , Yury Uralsky , Magnus Andersson , Marco Salvi , Christoph Kubisch
Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.
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Patent Agency Ranking
公开(公告)号：US12198255B2
公开(公告)日：2025-01-14
申请号：US18471651
申请日：2023-09-21
Applicant: NVIDIA CORPORATION
Inventor： Samuli Laine , Timo Aila , Tero Karras , Gregory Muthler , William P. Newhall, Jr. , Ronald C Babich, Jr. , Craig Kolb , Ignacio Llamas , John Burgess
Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
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公开(公告)号：US12020367B2
公开(公告)日：2024-06-25
申请号：US17669430
申请日：2022-02-11
Applicant: NVIDIA Corporation
Inventor： Gregory Muthler , John Burgess , James Robertson , Magnus Anderson
CPC classification number: G06T15/06 , G06F9/5027 , G06T1/20 , G06T15/005 , G06T15/08 , G06T17/10 , G06T2210/12
Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.
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公开(公告)号：US11816783B2
公开(公告)日：2023-11-14
申请号：US17829954
申请日：2022-06-01
Applicant: NVIDIA Corporation
Inventor： Gregory Muthler , John Burgess
CPC classification number: G06T15/06 , G06F9/30094 , G06F9/5027 , G06T15/08 , G06T17/005 , G06T2210/12
Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.
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公开(公告)号：US11804000B2
公开(公告)日：2023-10-31
申请号：US17513023
申请日：2021-10-28
Applicant: NVIDIA CORPORATION
Inventor： Samuli Laine , Timo Aila , Tero Karras , Gregory Muthler , William P. Newhall, Jr. , Ronald C. Babich, Jr. , Craig Kolb , Ignacio Llamas , John Burgess
CPC classification number: G06T15/06 , G06T15/005 , G06T17/005
Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
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公开(公告)号：US11302056B2
公开(公告)日：2022-04-12
申请号：US16897909
申请日：2020-06-10
Applicant: NVIDIA Corporation
Inventor： Gregory Muthler , John Burgess
Abstract: Ray tracing hardware accelerators supporting multiple specifiers for controlling the traversal of a ray tracing acceleration data structure are disclosed. For example, traversal efficiency and complex ray tracing effects can be achieved by specifying traversals through such data structures using both programmable ray operations and explicit node masking. The explicit node masking utilizes dedicated fields in the ray and in nodes of the acceleration data structure to control traversals. Ray operations, however, are programmable per ray using opcodes and additional parameters to control traversals. Traversal efficiency is improved by enabling more aggressive culling of parts of the data structure based on the combination of explicit node masking and programmable ray operations. More complex ray tracing effects are enabled by providing for dynamic selection of nodes based on individual ray characteristics.
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