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公开(公告)号:US12198253B2
公开(公告)日:2025-01-14
申请号:US18239876
申请日:2023-08-30
Applicant: NVIDIA Corporation
Inventor: Samuli Laine , Tero Karras , Greg Muthler , William Parsons Newhall, Jr. , Ronald Charles Babich, Jr. , Ignacio Llamas , John Burgess
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
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公开(公告)号:US11966737B2
公开(公告)日:2024-04-23
申请号:US17465234
申请日:2021-09-02
Applicant: NVIDIA Corporation
Inventor: Ronald Charles Babich, Jr. , John Burgess , Jack Choquette , Tero Karras , Samuli Laine , Ignacio Llamas , Gregory Muthler , William Parsons Newhall, Jr.
CPC classification number: G06F9/3004 , G06F9/3877 , G06F9/4843 , G06F15/163 , G06T1/20 , G06T1/60 , G06T2200/28
Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.
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公开(公告)号:US11675704B2
公开(公告)日:2023-06-13
申请号:US17483133
申请日:2021-09-23
Applicant: NVIDIA Corporation
Inventor: Greg Muthler , Timo Aila , Tero Karras , Samuli Laine , William Parsons Newhall, Jr. , Ronald Charles Babich, Jr. , John Burgess , Ignacio Llamas
IPC: G06F12/00 , G06F12/0875 , G06T15/06 , G06F16/901
CPC classification number: G06F12/0875 , G06F16/9027 , G06T15/06 , G06T2207/20021
Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.
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公开(公告)号:US11164360B2
公开(公告)日:2021-11-02
申请号:US16919700
申请日:2020-07-02
Applicant: NVIDIA Corporation
Inventor: Samuli Laine , Tero Karras , Greg Muthler , William Parsons Newhall , Ronald Charles Babich , Ignacio Llamas , John Burgess
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
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公开(公告)号:US10915364B2
公开(公告)日:2021-02-09
申请号:US15368434
申请日:2016-12-02
Applicant: Nvidia Corporation
Inventor: Stephen Jones , Philip Alexander Cuadra , Daniel Elliot Wexler , Ignacio Llamas , Lacky V. Shah , Jerome F. Duluk , Christopher Lamb
Abstract: Apparatuses, systems, and techniques for performing nested kernel execution within a parallel processing subsystem. In at least one embodiment, a parent thread launches a nested child grid on the parallel processing subsystem, and enables the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid.
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公开(公告)号:US20200349755A1
公开(公告)日:2020-11-05
申请号:US16935431
申请日:2020-07-22
Applicant: NVIDIA Corporation
Inventor: Shiqiu Liu , Christopher Ryan Wyman , Jon Hasselgren , Jacob Munkberg , Ignacio Llamas
Abstract: Disclosed approaches may leverage the actual spatial and reflective properties of a virtual environment—such as the size, shape, and orientation of a bidirectional reflectance distribution function (BRDF) lobe of a light path and its position relative to a reflection surface, a virtual screen, and a virtual camera—to produce, for a pixel, an anisotropic kernel filter having dimensions and weights that accurately reflect the spatial characteristics of the virtual environment as well as the reflective properties of the surface. In order to accomplish this, geometry may be computed that corresponds to a projection of a reflection of the BRDF lobe below the surface along a view vector to the pixel. Using this approach, the dimensions of the anisotropic filter kernel may correspond to the BRDF lobe to accurately reflect the spatial characteristics of the virtual environment as well as the reflective properties of the surface.
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公开(公告)号:US20170083373A1
公开(公告)日:2017-03-23
申请号:US15368434
申请日:2016-12-02
Applicant: Nvidia Corporation
Inventor: Stephen Jones , Philip Alexander Cuadra , Daniel Elliot Wexler , Ignacio Llamas , Lacky V. Shah , Jerome F. Duluk , Christopher Lamb
CPC classification number: G06F9/5027 , G06F9/522 , G06F2209/483 , G06T1/20
Abstract: One embodiment of the present invention sets forth a technique for performing nested kernel execution within a parallel processing subsystem. The technique involves enabling a parent thread to launch a nested child grid on the parallel processing subsystem, and enabling the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid. This technique advantageously enables the parallel processing subsystem to perform a richer set of programming constructs, such as conditionally executed and nested operations and externally defined library functions without the additional complexity of CPU involvement.
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公开(公告)号:US11727632B2
公开(公告)日:2023-08-15
申请号:US17376866
申请日:2021-07-15
Applicant: NVIDIA CORPORATION
Inventor: Martin Stich , Ignacio Llamas , Steven Parker
CPC classification number: G06T15/83 , G06F9/54 , G06T15/005 , G06T15/06
Abstract: In various examples, shader bindings may be recorded in a shader binding table that includes shader records. Geometry of a 3D scene may be instantiated using object instances, and each may be associated with a respective set of the shader records using a location identifier of the set of shader records in memory. The set of shader records may represent shader bindings for an object instance under various predefined conditions. One or more of these predefined conditions may be implicit in the way the shader records are arranged in memory (e.g., indexed by ray type, by sub-geometry, etc.). For example, a section selector value (e.g., a section index) may be computed to locate and select a shader record based at least in part on a result of a ray tracing query (e.g., what sub-geometry was hit, what ray type was traced, etc.).
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公开(公告)号:US11645810B2
公开(公告)日:2023-05-09
申请号:US17520100
申请日:2021-11-05
Applicant: NVIDIA Corporation
Inventor: Greg Muthler , Tero Karras , Samuli Laine , William Parsons Newhall, Jr. , Ronald Charles Babich, Jr. , John Burgess , Ignacio Llamas
IPC: G06T15/06
CPC classification number: G06T15/06
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.
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公开(公告)号:US20220327765A1
公开(公告)日:2022-10-13
申请号:US17852132
申请日:2022-06-28
Applicant: NVIDIA Corporation
Inventor: Shiqiu Liu , Christopher Ryan Wyman , Jon Hasselgren , Jacob Munkberg , Ignacio Llamas
Abstract: Disclosed approaches may leverage the actual spatial and reflective properties of a virtual environment—such as the size, shape, and orientation of a bidirectional reflectance distribution function (BRDF) lobe of a light path and its position relative to a reflection surface, a virtual screen, and a virtual camera—to produce, for a pixel, an anisotropic kernel filter having dimensions and weights that accurately reflect the spatial characteristics of the virtual environment as well as the reflective properties of the surface. In order to accomplish this, geometry may be computed that corresponds to a projection of a reflection of the BRDF lobe below the surface along a view vector to the pixel. Using this approach, the dimensions of the anisotropic filter kernel may correspond to the BRDF lobe to accurately reflect the spatial characteristics of the virtual environment as well as the reflective properties of the surface.
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