公开(公告)号：US20110055466A1

公开(公告)日：2011-03-03

申请号：US12941710

申请日：2010-11-08

申请人： Yasuo KUDO ,  Hiroshi Sukegawa ,  Kazuya Kawamoto

发明人： Yasuo KUDO ,  Hiroshi Sukegawa ,  Kazuya Kawamoto

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C16/10

摘要： A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.

公开(公告)号：US07890732B2

公开(公告)日：2011-02-15

申请号：US11945187

申请日：2007-11-26

申请人： Hiroshi Sukegawa

发明人： Hiroshi Sukegawa

IPC分类号： G06F9/26 ,  G06F9/34

CPC分类号： G06F12/0246 ,  G11C16/102

摘要： A memory card includes a controller and a nonvolatile semiconductor memory. The controller manages a correspondence between a first address in a semiconductor memory of a first erase block size and a second address in a semiconductor memory of a second erase block size other than the first erase block size. The nonvolatile semiconductor memory is a memory of the second erase block size. The controller executes access to the nonvolatile semiconductor memory by the second address.

摘要翻译： 存储卡包括控制器和非易失性半导体存储器。 控制器管理第一擦除块大小的半导体存储器中的第一地址与第一擦除块大小之外的第二擦除块大小的半导体存储器中的第二地址之间的对应关系。 非易失性半导体存储器是第二擦除块大小的存储器。 控制器通过第二地址执行对非易失性半导体存储器的访问。

公开(公告)号：US20100217919A1

公开(公告)日：2010-08-26

申请号：US12551898

申请日：2009-09-01

申请人： Hiroshi Sukegawa ,  Hidetaka Tsuji ,  Shuji Takano

发明人： Hiroshi Sukegawa ,  Hidetaka Tsuji ,  Shuji Takano

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/1032 ,  G11C16/349

摘要： A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

摘要翻译： 存储器控制器包括逻辑物理地址转换表，访问号码存储部，被配置为存储与逻辑地址相关联地从存储器单元读出数据的访问次数;存储状态检查部，被配置为检查存储状态 如果数据的存储状态处于预定的降级状态，则刷新处理部被配置为执行刷新处理以恢复存储在存储单元中的数据。

公开(公告)号：US20090324020A1

公开(公告)日：2009-12-31

申请号：US12540886

申请日：2009-08-13

申请人： Mitsutake Hasebe ,  Hiroshi Sukegawa ,  Kei Takizawa ,  Yasuhiro Aoki

发明人： Mitsutake Hasebe ,  Hiroshi Sukegawa ,  Kei Takizawa ,  Yasuhiro Aoki

IPC分类号： G06K9/00

CPC分类号： G06T7/00 ,  G06K9/00228 ,  G06K9/00926 ,  G06K9/036 ,  G06K9/6214

摘要： In a person retrieval apparatus, a plurality of extraction processing sections each extract personal biometric information from images taken by a plurality of cameras. A quality determination section determines a quality of each piece of biometric information extracted by the extraction processing sections. A reliability level setting section sets a reliability level to each piece of biometric information on the basis of the quality determined by the quality determination section. The biometric information extracted by the extraction processing sections and the reliability level set by the reliability level setting section are stored in a memory. In this state, in the person retrieval apparatus, the face retrieval section performs person retrieval processing on each piece of biometric information stored in the memory in descending order of the reliability level corresponding to each piece of biometric information.

摘要翻译： 在个人检索装置中，多个提取处理部分从多个照相机拍摄的图像中提取个人生物信息。 质量确定部确定由提取处理部分提取的每条生物信息的质量。 可靠性水平设定部根据由质量决定部确定的质量，对每条生物信息设定可靠性水平。 由提取处理部分提取的生物特征信息和由可靠性等级设置部分设置的可靠性等级被存储在存储器中。 在该状态下，在人物检索装置中，面部检索部按照与每条生物体信息对应的可靠度水平的降序对存储在存储器中的每条生物体信息进行人物检索处理。

公开(公告)号：US07616507B2

公开(公告)日：2009-11-10

申请号：US11838463

申请日：2007-08-14

申请人： Hiroshi Sukegawa ,  Kenji Sakaue ,  Hitoshi Tsunoda

发明人： Hiroshi Sukegawa ,  Kenji Sakaue ,  Hitoshi Tsunoda

IPC分类号： G11C7/00

CPC分类号： G11C11/5642 ,  G06F9/4403 ,  G11C16/0483 ,  G11C16/20 ,  G11C29/74 ,  G11C2211/5641

摘要： A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a corresponding one of the word lines and each having N threshold voltages for storing multi-valued level, where N is a natural number of 4 or greater; wherein stored data in each of the plurality of memory cells constitutes a plurality of pages, at least only a part of multi-value level is used for storing data, a data “1” is always written to a lower page, a “0” or “1” binary data is written to an upper page, the same data is written in each of the pages when writing in the nonvolatile memory device, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory device.

摘要翻译： 一种包括非易失性半导体存储器件和控制器的存储器系统。 存储装置包括多个字线; 以及多个存储单元，每个存储单元连接到对应的一条字线，并且每个具有用于存储多值电平的N个阈值电压，其中N是4或更大的自然数; 其中，所述多个存储单元的每一个中存储的数据构成多个页面，至少只有一部分多值级别用于存储数据，数据“1”总是写入下页，“0” 或“1”二进制数据被写入上部页面时，在写入非易失性存储器件时，在每个页面中写入相同的数据，并且只有读取相同数据的页面的一部分才被读取 非易失性存储器件。

公开(公告)号：US07558148B2

公开(公告)日：2009-07-07

申请号：US11776037

申请日：2007-07-11

申请人： Hiroshi Sukegawa ,  Takeshi Nakano

发明人： Hiroshi Sukegawa ,  Takeshi Nakano

IPC分类号： G11C8/00

CPC分类号： G06F13/1668 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C2211/5641

摘要： A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.

摘要翻译： 一种用于在包括具有串联电流路径和电荷存储层的多个存储单元的第一半导体存储器中写入数据的存储器控​​制器包括被配置为可接收来自主机设备的第一数据的主机接口，临时的第二半导体存储器 保存第二数据，以及根据第一半导体存储器的状态生成第二数据的运算单元，将第二数据临时保存在第二半导体存储器中，并将第一和第二数据写入第一半导体存储器。 当写入第二数据时，运算单元不选择与选择栅极线相邻的字线，并且选择不与选择栅极线相邻的字线。

公开(公告)号：US07266224B2

公开(公告)日：2007-09-04

申请号：US10647744

申请日：2003-08-26

申请人： Hiroshi Sukegawa

发明人： Hiroshi Sukegawa

IPC分类号： G06K9/00

CPC分类号： G06K9/00288 ,  G06K9/00926 ,  G06K9/6255

摘要： A person recognizing apparatus inputs a face image of a person subject to recognition through a camera and obtains the similarity of this input face image with the registered information stored in the registered information memory pre-storing face images of recognized persons by collating them by the recognizer. Therefore, in this person recognizing apparatus to recognize a said person based on the obtained similarity, a registered information updating unit judges whether the similarity obtained by a recognizer is within a prescribed updating range and updates a registered information stored in the registered information memory based on the face image input by the camera based on being judged as the similarity is in the prescribed updating range.

摘要翻译： 人物识别装置通过照相机输入被识别人的面部图像，并且通过识别器将它们与存储在已登记信息存储器预存储面部图像中的登记信息进行对照，从而获得该识别者的相似度 。 因此，在该人识别装置中，基于所获得的相似度来识别所述人物，登记信息更新单元判断由识别器获得的相似度是否在规定的更新范围内，并且基于存储在登记信息存储器中的登记信息进行更新 基于被判断为相似度的照相机输入的脸部图像在规定的更新范围内。

公开(公告)号：US20060274566A1

公开(公告)日：2006-12-07

申请号：US11443388

申请日：2006-05-31

申请人： Daisaburo Takashima ,  Shuso Fujii ,  Takaya Suda ,  Hiroshi Sukegawa

发明人： Daisaburo Takashima ,  Shuso Fujii ,  Takaya Suda ,  Hiroshi Sukegawa

IPC分类号： G11C11/22

CPC分类号： G11C14/00 ,  G06F12/0246 ,  G06F2212/7207 ,  G11C7/1075 ,  G11C11/22 ,  G11C16/0483

摘要： A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.

摘要翻译： 存储器系统包括通过布置具有铁电电容器和单元晶体管的多个存储单元形成的铁电存储器，通过布置具有浮动栅极并能够电擦除和写入数据的多个存储单元形成的快闪EEPROM，控制电路 被配置为控制铁电存储器和闪存EEPROM，以及被配置为与外部通信的接口电路。 闪存EEPROM存储数据。 铁电存储器存储用于存储数据的根信息，目录信息，数据的文件名，数据的文件大小，存储数据的存储位置的文件分配表信息和写入完成时间中的至少一个 数据。

公开(公告)号：US07120278B2

公开(公告)日：2006-10-10

申请号：US10226329

申请日：2002-08-23

申请人： Hiroshi Sukegawa ,  Kentaro Yokoi ,  Hironori Dobashi ,  Jun Ogata ,  Toshio Sato ,  Akio Okazaki

发明人： Hiroshi Sukegawa ,  Kentaro Yokoi ,  Hironori Dobashi ,  Jun Ogata ,  Toshio Sato ,  Akio Okazaki

IPC分类号： G06K9/00

CPC分类号： G06K9/00288 ,  G06K9/6255

摘要： When authentication data of a person O to be authenticated is registered as dictionary data, this authentication data of the person to be authenticated is acquired and collated with the registered dictionary data. In accordance with the collation result, the dictionary data is updated.

公开(公告)号：US20060126906A1

公开(公告)日：2006-06-15

申请号：US11339533

申请日：2006-01-26

申请人： Toshio Sato ,  Akio Okazaki ,  Hiroshi Sukegawa ,  Jun Ogata

发明人： Toshio Sato ,  Akio Okazaki ,  Hiroshi Sukegawa ,  Jun Ogata

IPC分类号： G06K9/00 ,  G05B19/00

CPC分类号： G07C9/00166 ,  G06K9/00288 ,  G07C9/00158

摘要： Feature amounts of faces of visitors photographed at a first gate are registered in a registration section in relation to entrance permission time information items each of which defines a period of time during which entrance through a second gate provided inside the first gate is permitted. At the second gate, the face of the visitor is photographed and the feature amount of the photographed face of the visitor is collated with the face feature amounts registered in the registration section. Entrance through the second gate is controlled based on the result of collation and the entrance permission time information registered in the registration section.