公开(公告)号：US5526348A

公开(公告)日：1996-06-11

申请号：US310080

申请日：1994-09-22

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04J1/00 ,  H04B7/212 ,  H04W72/04 ,  H04W74/00 ,  H04W76/02 ,  H04B7/208

CPC classification number: H04W76/02 ,  H04B7/2123 ,  H04W72/04 ,  H04W74/00

Abstract: To establish radio channels according to a DAMA scheme, FDM radio channels are divided into channel groups, each containing a predetermined number of neighboring channels. The base station includes group modems for FDM modem processing, on a basis of each channel group, into uplink baseband signals uplink radio signals received from source stations in uplink channel groups and downlink baseband signals into downlink radio signals sent to destination stations in downlink channel groups and a switching unit for switching the baseband signals from the uplink channel groups into the downlink channel groups according to the destination stations. Each terminal station includes a group modem for FDM modem processing en-bloc downlink channel group radio signals into downlink terminal baseband signals and uplink terminal baseband signals into uplink channel group radio signals and baseband processors for processing the downlink terminal baseband signals for supply to the communication terminals according to the neighboring channels of the downlink channel group and uplink baseband signals of the communication terminals into the uplink terminal baseband signals according to the neighboring channels of the uplink channel group.

Abstract translation: 为了根据DAMA方案建立无线电信道，FDM无线电信道被分成信道组，每个信道组包含预定数量的相邻信道。 基站包括用于FDM调制解调器处理的组调制解调器，在每个信道组的基础上，将上行链路信道组中的源站接收的上行无线信号和下行链路基带信号的上行链路信号转换成下行链路信道组中发送到目的站的下行无线信号 以及用于根据目的站将来自上行链路信道组的基带信号切换成下行链路信道组的切换单元。 每个终端包括用于FDM调制解调器的组调制解调器将下行链路信道组无线电信号转换成下行链路终端基带信号和上行链路终端基带信号转换成上行链路信道组无线电信号和基带处理器，用于处理下行链路终端基带信号以供给通信 根据上行链路信道组的相邻信道，根据下行链路信道组的相邻信道的终端和通信终端的上行链路基带信号进入上行链路终端基带信号。

公开(公告)号：US5311555A

公开(公告)日：1994-05-10

申请号：US954664

申请日：1992-09-30

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H03H17/08 ,  H04L27/00 ,  H04L27/22 ,  H04L27/227 ,  H04L27/233 ,  H03D3/22

CPC classification number: H04L27/2332 ,  H04L2027/003 ,  H04L2027/0048 ,  H04L2027/0057

Abstract: In a phase divider, a complex signal containing a sequence of samples of real and imaginary values is limited to a unit amplitude and multiplied by a first complex multiplier with a first feedback complex signal, the output the multiplier being fed through a loop filter to a second complex multiplier where the signal is multiplied with a second feedback complex signal. The output of the second multiplier is limited to a unit amplitude, delayed by a sample interval and applied to the second complex multiplier as the second feedback complex signal. The first feedback complex signal is derived by a circuit that raises the frequency the delayed signal by a desired factor.

Abstract translation: 在相位分配器中，包含实数和虚数值样本序列的复信号被限制为单位幅度并乘以具有第一反馈复信号的第一复数乘法器，乘法器通过环路滤波器馈送到 第二复数乘法器，其中信号与第二反馈复信号相乘。 第二乘法器的输出被限制为单位幅度，延迟采样间隔并作为第二反馈复信号施加到第二复数乘法器。 第一反馈复信号由电路导出，该电路将延迟信号的频率提高了期望的因子。

公开(公告)号：US5270665A

公开(公告)日：1993-12-14

申请号：US947603

申请日：1992-09-21

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04L27/227 ,  H04L27/00 ,  H04L27/22 ,  H04L27/233 ,  H03D3/00

CPC classification number: H04L27/2332 ,  H04L2027/003 ,  H04L2027/0048

Abstract: For processing a multiplied signal into a modified signal in a demodulator circuit, an adder (34) sums up a first, a second, and a third processed signal into a sum signal for use as the modified signal. A first processing circuit (31) processes the multiplied signal into the first processed signal. A second processing circuit (32) processes the multiplied signal into the second processed signal in accordance with a conjugate complex clock and a complex local signal. A third signal processing circuit (33) processes the multiplied signal into the third processed signal in accordance with a complex clock and a conjugate complex local signal. The complex clock signal represents a first complex number. The complex local signal represents a second complex number. The conjugate complex clock signal represents a complex conjugate of the first complex number. The conjugate complex local signal represents a complex conjugate of the second complex number.

公开(公告)号：US5173663A

公开(公告)日：1992-12-22

申请号：US782644

申请日：1991-10-25

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04L27/227 ,  H03L7/099 ,  H04L7/00 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033 ,  H04L27/00 ,  H04L27/22 ,  H04L27/233

CPC classification number: H04L7/0029 ,  H03L7/0994 ,  H04L27/2332 ,  H04L7/0278 ,  H04L2027/003 ,  H04L2027/0048

Abstract: A digital output of a quasi-coherent detection circuit is M-th power multiplied and then processed by a set of digital filters to generate signals for coherent detection and clock interpolation. The digital output of the quasi-coherent detection circuit is also fed, through a delay circuit, a coherent detection circuit which in turn processes the digital output of the quasi-coherent detection circuit, using the coherent detection signal. Timing error information indicative of the difference between phases of an interpolated clock and the interpolation signal determines the weighting factor of data interpolation channel filter which in turn interpolate and output coherent-detected data signal.

公开(公告)号：US5119037A

公开(公告)日：1992-06-02

申请号：US704531

申请日：1991-05-23

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H03D13/00 ,  H03H17/02 ,  H03L7/00

CPC classification number: H03D13/00 ,  H03H17/0202 ,  H03L7/00

Abstract: A phase-lock loop device for phase locking a device input signal representing a first complex number and having a device input phase which should be locked into a locked phase, includes the following. A first complex multiplier to calculate a first product of the first complex number and a first conjugate complex number to produce a first complex product signal. The first conjugate complex number is represented by a first conjugate signal which is produced by delaying and processing the device input signal. A second complex multiplier to calculate a second product of a phase processed signal and a multiplier input signal to produce a second complex product signal. The phase processed signal is produced by filtering and processing the first complex product signal. The multiplier input signal is produced by delaying and limiting the second complex product signal. A third complex multiplier to calculate a third product of the first complex number and a second conjugate complex number to produce a third complex product signal. The second conjugate complex number is represented by a second conjugate signal which is produced by processing the second complex product signal. A fourth complex multiplier to calculate a fourth product of the second complex product signal and a filtered signal to produce a fourth complex product signal having the locked phase. the filtered signal is produced by filtering the third complex product signal.

公开(公告)号：US4905221A

公开(公告)日：1990-02-27

申请号：US236019

申请日：1988-08-24

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04B7/216 ,  H04J13/00

CPC classification number: H04B7/216

Abstract: For use in a satellite communication system which carries out communication through a satellite by the use of an up-link frequency band and a down-link frequency band, each of the up-link and the down-link frequency bands has a plurality of frequency subbands spaced apart from one another with frequency gap bands interposed between the frequency subbands. An earth station comprises a modulating arrangement (47) for modulating a selected one of the frequency subbands of the up-link frequency band by a first input signal into a subband transmission signal; a first transmitting arrangement (51) coupled to the modulating arrangement for transmitting the subband transmission signal through the selected one of the frequency subbands; a spread spectrum processing arrangement (50) for processing a second input signal into a spread spectrum transmission signal in the up-link frequency band; and a second transmitting arrangement (51) coupled to the spread spectrum processing arrangement for transmitting the spread spectrum transmission signal through the up-link frequency band.

公开(公告)号：US4654864A

公开(公告)日：1987-03-31

申请号：US486576

申请日：1983-04-19

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04B1/26 ,  H03L7/10 ,  H03L7/113 ,  H04L27/227 ,  H03D3/24

CPC classification number: H04L27/2272 ,  H03L7/10

Abstract: A fast pull-in phase synchronizing circuit, including a phaselock loop, having an extended pull-in range. The phase synchronizing circuit includes, besides a conventional phaselock loop, at least a .pi./2+n.pi. (n being an integer) phase shifter, a mixer, a low pass filter and another mixer. The phase shifter receives the output of the phaselock loop VCO, the output of the phase shifter being multiplied in the mixer with the circuit input signal. This multiplied signal is applied as an input to the low pass filter, which produces a low frequency output proportional to the frequency difference between the input and output signals. This low frequency signal is mixed in the other mixer with the circuit input signal to produce the phaselock loop input signal. The phaselock loop input is phase compared with the VCO output in the phaseback loop phase comparator. This phase comparator output has by reason of the phase synchronizing circuit of the invention two components, one representing the frequency discrimination characteristic of the circuit, the other the phase comparison characteristic. When in its unsynchronized state, the circuit of the invention operates as an automatic frequency control circuit causing the VCO oscillating frequency to vary in a direction to decrease the frequency error, W.sub.in -W.sub.ont. Once the frequency error has been reduced to the pull-in range, i.e. the synchronized range, the circuit of the invention operates to produce phase synchronization.

Abstract translation: 包括具有延长拉入范围的锁相环的快速拉入相位同步电路。 除了传统的锁相环外，相位同步电路还包括至少一个pi / 2 + n pi（n为整数）移相器，混频器，低通滤波器和另一个混频器。 移相器接收锁相环VCO的输出，移相器的输出在混频器中与电路输入信号相乘。 该倍增信号作为低通滤波器的输入端被施加，该低通滤波器产生与输入和输出信号之间的频率差成比例的低频输出。 该低频信号在另一个混频器中与电路输入信号混合，以产生锁相环输入信号。 相位环路输入与相位回路相位比较器中的VCO输出相位相位相位。 该相位比较器输出是由于本发明的相位同步电路的两个部件，一个表示电路的频率鉴别特性，另一个是相位比较特性。 当处于非同步状态时，本发明的电路作为自动频率控制电路工作，使得VCO振荡频率在降低频率误差的方向上变化，Win-Wont。 一旦频率误差已经降低到拉入范围，即同步范围，本发明的电路就可以产生相位同步。