公开(公告)号：US06983265B2

公开(公告)日：2006-01-03

申请号：US10316250

申请日：2002-12-10

Applicant: Pascal Tannhof ,  Ghislain Imbert de Tremiolles

Inventor： Pascal Tannhof ,  Ghislain Imbert de Tremiolles

IPC: G06N3/06

CPC classification number: G06K9/6276 ,  G06N3/04

Abstract: A method is described to improve the data transfer rate between a personal computer or a host computer and a neural network implemented in hardware by merging a plurality of input patterns into a single input pattern configured to globally represent the set of input patterns. A base consolidated vector (U′*n) representing the input pattern is defined to describe all the vectors (Un, . . . , Un+6) representing the input patterns derived thereof (U′n, . . . , U′n+6) by combining components having fixed and ‘don't care’ values. The base consolidated vector is provided only once with all the components of the vectors. An artificial neural network (ANN) is then configured as a combination of sub-networks operating in parallel. In order to compute the distances with an adequate number of components, the prototypes are to include also components having a definite value and ‘don't care’ conditions. During the learning phase, the consolidated vectors are stored as prototypes. During the recognition phase, when a new base consolidated vector is provided to ANN, each sub-network analyses a portion thereof After computing all the distances, they are sorted one sub-network at a time to obtain the distances associated to each vector.

Abstract translation: 描述了一种方法，以通过将多个输入模式合并为被配置为全局地表示该组输入模式的单个输入模式来改善个人计算机或主机计算机与硬件中实现的神经网络之间的数据传输速率。 定义表示输入模式的基本合并向量（U'* N n N）来描述所有向量（U N，N，N，N，N） 代表其导出的输入模式（U'，N“，...，U”n + 6）的组合，通过组合具有固定的“不” 护理价值观。 基本合并向量仅与向量的所有分量一起提供。 然后将人造神经网络（ANN）配置为并行操作的子网络的组合。 为了用足够数量的组件计算距离，原型还包括具有确定值和“无关紧要”条件的组件。 在学习阶段，合并的向量存储为原型。 在识别阶段，当向ANN提供新的基本合并向量时，每个子网络分析其一部分。在计算所有距离之后，它们一次对一个子网进行排序，以获得与每个向量相关联的距离。

公开(公告)号：US5740326A

公开(公告)日：1998-04-14

申请号：US486658

申请日：1995-06-07

Applicant: Jean-Yves Boulet ,  Pascal Tannhof ,  Guy Paillet

Inventor： Jean-Yves Boulet ,  Pascal Tannhof ,  Guy Paillet

IPC: G06F15/18 ,  G06F7/544 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063

CPC classification number: G06K9/6271 ,  G06F7/544 ,  G06N3/063 ,  G06K2209/01

Abstract: In a neural network of N neuron circuits, having an engaged neuron's calculated p bit wide distance between an input vector and a prototype vector and stored in the weight memory thereof, an aggregate search/sort circuit (517) of N engaged neurons' search/sort circuits. The aggregate search/sort circuit determines the minimum distance among the calculated distances. Each search/sort circuit (502-1) has p elementary search/sort units connected in series to form a column, such that the aggregate circuit is a matrix of elementary search/sort units. The distance bit signals of the same bit rank are applied to search/sort units in each row. A feedback signal is generated by ORing in an OR gate (12.1) all local search/sort output signals from the elementary search/sort units of the same row. The search process is based on identifying zeroes in the distance bit signals, from the MSB's to the LSB's. As a zero is found in a row, all the columns with a one in that row are excluded from the subsequent row search. The search process continues until only one distance, the minimum distance, remains and is available at the output of the OR circuit. The above described search/sort circuit may further include a latch allowing the aggregate circuit to sort remaining distances in increasing order.

Abstract translation: 在N个神经元电路的神经网络中，在输入向量和原型向量之间具有被约束的神经元计算的p位宽的距离并存储在其权重存储器中，N个接收的神经元的搜索/ 排序电路。 聚合搜索/分类电路确定计算出的距离之间的最小距离。 每个搜索/分类电路（502-1）具有串联连接的p个基本搜索/分类单元以形成列，使得聚合电路是基本搜索/分类单元的矩阵。 相同位等级的距离位信号被应用于每行的搜索/排序单元。 通过在或门（12.1）中对来自同一行的基本搜索/排序单元的所有本地搜索/排序输出信号进行“或”生成反馈信号。 搜索过程基于识别距离位信号中的零，从MSB到LSB。 由于在一行中找到零，所以在该行中具有一个列的列将从后续行搜索中排除。 搜索过程继续，直到只有一个距离，最小距离保持，并且在OR电路的输出端可用。 上述搜索/分类电路还可以包括允许聚合电路以增加的顺序对剩余距离进行排序的锁存器。

公开(公告)号：US5621863A

公开(公告)日：1997-04-15

申请号：US481591

申请日：1995-06-07

Applicant: Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

Inventor： Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC: G06F15/18 ,  G06K9/66 ,  G06N3/00 ,  G06N3/06 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06K9/6272 ,  G06K9/00986 ,  G06N3/063

Abstract: In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector. A minimum distance determination circuit determines the minimum distance Dmin among all the calculated distances from all of the neuron circuits of the neural network and generates a local output signal of the distance type. The circuit may be used to search and sort categories. The feed-back signal is collectively generated by all the neuron circuits by ORing all the local distances/categories. A daisy chain circuit is serially connected to corresponding daisy chain circuits of two adjacent neuron circuits to chain the neurons together. The daisy chain circuit also determines the neuron circuit state as free or engaged. Finally, a context circuitry enables or inhibits neuron participation with other neuron circuits in generation of the feedback signal.

Abstract translation: 在由多个神经元电路组成的神经网络中，生成本地结果信号的改进的神经元电路，例如， 的火灾类型，以及距离或类别类型的本地输出信号。 连接到传送输入数据（例如输入类别）和控制信号的总线的神经元电路。 多范围距离评估电路计算输入矢量和存储在R / W存储器电路中的原型矢量之间的距离D. 距离比较电路将该距离D与存储的原型矢量的实际影响场或其下限进行比较，以产生第一和第二比较信号。 识别电路处理比较信号，输入类别信号，局部类别信号和反馈信号，以产生表示神经元电路对输入矢量的响应的本地结果信号。 最小距离确定电路确定来自神经网络的所有神经元电路的所有计算距离中的最小距离Dmin，并产生距离类型的局部输出信号。 该电路可用于搜索和分类。 所有的神经元电路通过对所有的局部距离/类别进行OR运算来共同地产生反馈信号。 菊花链电路串联连接到两个相邻神经元电路的相应菊花链电路，以将神经元链接在一起。 菊花链电路还将神经元电路状态确定为自由或接合。 最后，上下文电路在反馈信号的产生中实现或抑制与其他神经元电路的神经元参与。

公开(公告)号：US08609530B2

公开(公告)日：2013-12-17

申请号：US13052262

申请日：2011-03-21

Applicant: Simon Jeannot ,  Pascal Tannhof

Inventor： Simon Jeannot ,  Pascal Tannhof

IPC: H01L21/4763

CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.

Abstract translation: 一种用于在包括一系列金属水平和通孔级别的互连堆叠的金属层中形成电容结构的方法，包括以下步骤：在金属层面形成至少一个其中限定沟槽的导电轨道; 在结构上保形地形成绝缘层; 在沟槽中形成导电材料; 并平坦化结构。

公开(公告)号：US20050154802A1

公开(公告)日：2005-07-14

申请号：US10757187

申请日：2004-01-14

Applicant: Kerry Kravec ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

Inventor： Kerry Kravec ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

IPC: G06F3/00 ,  G06K9/00 ,  G06K9/64

CPC classification number: G06K9/6202 ,  G06K9/00986

Abstract: A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.

Abstract translation: 并行模式检测引擎（PPDE）包括定制的多个处理单元（PU），以执行各种模式识别模式。 PU装载有不同的图案，并且要匹配的输入数据并行提供给PU。 每个模式都有一个操作码，定义当输入数据流中的特定数据与时钟周期中正在比较的对应数据匹配或不匹配时要执行的操作。 每个PU通信所选择的信息，使得PU可以被级联以使得能够匹配更长的模式或允许针对特定的输入数据流并行地处理更多的模式。

公开(公告)号：US20050138324A1

公开(公告)日：2005-06-23

申请号：US10905100

申请日：2004-12-15

Applicant: Pascal Tannhof ,  Jan Slyfield

Inventor： Pascal Tannhof ,  Jan Slyfield

IPC: G06F15/00 ,  G06F15/173

CPC classification number: G06F15/17368

Abstract: A processing unit having a dual channel bus architecture associated with a specific instruction set, configured to receive an input message and transmit an output message that is identical or derived therefrom. A message consists of one opcode, with or without associated data, used to control each processing unit depending on logic conditions stored in dedicated registers in each unit. Processing units are serially connected but can work simultaneously for a total pipelined operation. This dual architecture is organized around two channels labeled Channel 1 and Channel 2. Channel 1 mainly transmits an input message to all units while Channel 2 mainly transmits the results after processing in a unit as an output message. Depending on the logic conditions, an input message not processed in a processing unit may be transmitted to the next one without any change.

Abstract translation: 一种具有与特定指令集相关联的双通道总线架构的处理单元，其被配置为接收输入消息并发送相同或从其导出的输出消息。 消息由一个操作码组成，具有或不具有关联数据，用于根据存储在每个单元中的专用寄存器中的逻辑条件来控制每个处理单元。 处理单元串联连接，但可以同时工作进行总体流水线操作。 该双重架构围绕标记为通道1和通道2的两个通道组合。通道1主要向所有单元发送输入消息，而通道2主要在以单元处理之后将结果作为输出消息发送。 根据逻辑条件，在处理单元中未处理的输入消息可以被发送到下一个，而没有任何改变。

公开(公告)号：US06782373B2

公开(公告)日：2004-08-24

申请号：US09682035

申请日：2001-07-12

Applicant: Ghislain Imbert de Tremiolles ,  Pascal Tannhof

Inventor： Ghislain Imbert de Tremiolles ,  Pascal Tannhof

IPC: G06N302

CPC classification number: G06K9/6215 ,  G06K9/6276 ,  G06N3/063

Abstract: The method and circuits of the present invention aim to associate a norm to each component of an input pattern presented to an input space mapping algorithm based artificial neural network (ANN) during the distance evaluation process. The set of norms, referred to as the “component” norms is memorized in specific memorization means in the ANN. In a first embodiment, the ANN is provided with a global memory, common for all the neurons of the ANN, that memorizes all the component norms. For each component of the input pattern, all the neurons perform the elementary (or partial) distance calculation with the corresponding prototype components stored therein during the distance evaluation process using the associated component norm. The distance elementary calculations are then combined using a “distance” norm to determine the final distance between the input pattern and the prototypes stored in the neurons. In another embodiment, the set of component norms is memorized in the neurons themselves in the prototype memorization means, so that the global memory is no longer physically necessary. This implementation allows to significantly optimize the consumed silicon area when the ANN is integrated in a silicon chip.

Abstract translation: 本发明的方法和电路旨在将距离评估过程中给出的输入模式的每个分量与基于输入空间映射算法的人造神经网络（ANN）相关联。 被称为“组件”规范的一套规范被记录在ANN中的具体记忆手段中。 在第一实施例中，ANN被提供有存储ANN的所有神经元的全局存储器，其存储所有的分量规范。 对于输入模式的每个分量，所有神经元使用相关的分量范数在距离评估过程中，使用存储在其中的对应的原型分量执行基本（或部分）距离计算。 然后使用“距离”范数组合距离基本计算，以确定输入模式和存储在神经元中的原型之间的最终距离。 在另一个实施例中，组件规范的集合被存储在原型存储装置中的神经元本身中，使得全局存储器不再是物理上必需的。 当ANN集成在硅芯片中时，该实现允许显着优化消耗的硅面积。

公开(公告)号：US06748405B2

公开(公告)日：2004-06-08

申请号：US09754639

申请日：2001-01-04

Applicant: Ghislain Imbert de Tremiolles ,  Didier Louis ,  Pascal Tannhof

Inventor： Ghislain Imbert de Tremiolles ,  Didier Louis ,  Pascal Tannhof

IPC: G06F700

CPC classification number: G06F7/544 ,  G06F7/22 ,  G06F9/30021

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=K×n). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a “thermometric” coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.

Abstract translation: 在搜索在q位上编码的p个编码集合中的最小值时，每个数字被分割为以n位编码的K个子值（q> = Kxn）。 因此，参数K为每个子值分配等级，使得形成K个比特片，其中每个切片由相同等级的子值组成。 然后使用“温度测量”编码技术，以m位（m> n）对每个子值进行编码。 然后对编码子值（MSB）的第一切片执行并行搜索以确定该切片的最小子值。 所有与子值相关联的数字大于已评估的最小子值的数字将被取消选择。 评估过程以相同的方式继续，直到最后一个切片（LSB）被处理。 在评估过程结束时，保持选中的数字具有最小值。 响应时间（即处理步骤的数目）现在只取决于数字已被分割的子值的数量K. 该方法也适用于搜索最大值。

公开(公告)号：US06622135B1

公开(公告)日：2003-09-16

申请号：US09465088

申请日：1999-12-16

Applicant: Gislain Imbert De Tremiolles ,  Pascal Tannhof ,  Erin Williams

Inventor： Gislain Imbert De Tremiolles ,  Pascal Tannhof ,  Erin Williams

IPC: G06N306

CPC classification number: G06K9/6276 ,  G06T7/0004 ,  G06T2207/30148

Abstract: To avoid the problem of category assignment in artificial neural networks (ANNs) based upon a mapping of the input space (like ROI and KNN algorithms), the present method uses “probabilities”. Now patterns memorized as prototypes do not represent categories any longer but the “probabilities” to belong to categories. Thus, after having memorized the most representative patterns in a first step of the learning phase, the second step consists of an evaluation of these probabilities. To that end, several counters are associated with each prototype and are used to evaluate the response frequency and accuracy for each neuron of the ANN. These counters are dynamically incremented during this second step using distances evaluation (between the input vectors and the prototypes) and error criteria (for example the differences between the desired responses and the response given by the ANN). At the end of the learning phase, a function of the contents of these counters allows an evaluation of these probabilities for each neuron to belong to predetermined categories. During the recognition phase, the probabilities associated with the neurons selected by the algorithm permit the characterization of new input vectors and more generally any kind of input (images, signals, sets of data) to detect and classify anomalies. The method allows a significant reduction in the number of neurons that are required in the ANN while improving its overall response accuracy.

Abstract translation: 为了避免基于输入空间（如ROI和KNN算法）的映射的人造神经网络（ANN）中的类别分配问题，本方法使用“概率”。 现在存储为原型的图案不再代表类别，而是属于类别的“概率”。 因此，在学习阶段的第一步中记住最具代表性的模式之后，第二步包括这些概率的评估。 为此，几个计数器与每个原型相关联，并用于评估ANN的每个神经元的响应频率和精度。 这些计数器在第二步使用距离评估（输入向量和原型之间）和错误标准（例如期望响应与ANN给出的响应之间的差异）进行动态递增。 在学习阶段结束时，这些计数器的内容的功能允许将每个神经元的这些概率的评估属于预定类别。 在识别阶段，与算法选择的神经元相关联的概率允许表征新的输入向量，更一般地，可以检测和分类异常的任何种类的输入（图像，信号，数据集）。 该方法允许在ANN中需要的神经元数目显着减少，同时提高其整体响应精度。

公开(公告)号：US06523018B1

公开(公告)日：2003-02-18

申请号：US09470459

申请日：1999-12-22

Applicant: Didier Louis ,  Pascal Tannhof ,  André Steimle

Inventor： Didier Louis ,  Pascal Tannhof ,  André Steimle

IPC: G06N306

CPC classification number: G06K9/6276 ,  G06N3/063

Abstract: The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input vector data, set-up parameters, etc., and signals such as the feed back and control signals. The R/W memory block, typically a RAM, is common to all neurons to avoid circuit duplication, increasing thereby the number of neurons integrated in the chip. The R/W memory stores the prototype components. Each neuron comprises a computation block, a register block, an evaluation block and a daisy chain block to chain the neurons. All these blocks (except the computation block) have a symmetric structure and are designed so that each neuron may operate in a dual manner, i.e. either as a single neuron (single mode) or as two independent neurons (dual mode). Each neuron generates local signals. The neural chip further includes an OR circuit which performs an OR function for all corresponding local signals to generate global signals that are merged in an on-chip common communication bus shared by all neurons of the chip. The R/W memory block, the neurons and the OR circuit form an artificial neural network having high flexibility due to this dual mode feature which allows to mix single and dual neurons in the ANN.

Abstract translation: 神经半导体芯片首先包括：全局寄存器和控制逻辑电路块，R / W存储器块和由传送诸如输入向量数据，建立参数等的数据的总线馈送的多个神经元，以及诸如 作为反馈和控制信号。 R / W存储器块（通常为RAM）对于所有神经元是共同的，以避免电路重复，从而增加集成在芯片中的神经元的数量。 R / W存储器存储原型组件。 每个神经元包括计算块，寄存器块，评估块和菊花链块以链接神经元。 所有这些块（计算块除外）具有对称结构，并且被设计成使得每个神经元可以以双重方式操作，即作为单个神经元（单个模式）或两个独立神经元（双模式）操作。 每个神经元产生本地信号。 所述神经芯片还包括OR电路，其对所有相应的本地信号执行OR功能，以产生合并在由所述芯片的所有神经元共享的片上公共通信总线中的全局信号。 R / W存储器块，神经元和OR电路形成具有高灵活性的人造神经网络，由于这种双模式特征，其允许在ANN中混合单个和双重神经元。