公开(公告)号：US08291266B2

公开(公告)日：2012-10-16

申请号：US12560088

申请日：2009-09-15

Applicant: David Windell ,  Pravin Patel ,  James Hughes ,  Christopher West ,  Robert Piper ,  Timothy Schlude

Inventor： David Windell ,  Pravin Patel ,  James Hughes ,  Christopher West ,  Robert Piper ,  Timothy Schlude

IPC: G06F11/00

CPC classification number: G06F11/325 ,  H04L41/0645

Abstract: Methods and systems for implementing such methods for providing server diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. Display of diagnostic service notifications may allow for completion of various service operations associated with service notifications once information specific to a fault is presented. Such service operations may include placing a system in standby mode, transferring workloads to other systems, initiating a firmware update, placing the system in a mode that allows for physical maintenance, or ordering parts associated with one or more faults.

Abstract translation: 用于实现用于提供服务器诊断和系统管理信息的这种方法的方法和系统可以包括但不限于：接收网络故障状态请求输入; 为具有一个或多个故障的一个或多个退化服务器节点照亮一个或多个服务器节点故障指示符; 接收具有一个或多个故障的劣化服务器节点的服务器节点故障状态请求输入; 以及显示针对所述退化服务器节点的一个或多个故障的一个或多个诊断服务通知。 诊断服务通知的显示可以允许一旦出现特定于故障的信息，完成与服务通知相关联的各种服务操作。 这样的服务操作可以包括将系统置于待机模式，将工作负载传输到其他系统，启动固件更新，将系统置于允许物理维护的模式中，或者订购与一个或多个故障相关联的部件。

公开(公告)号：US08249501B2

公开(公告)日：2012-08-21

申请号：US12114934

申请日：2008-05-05

Applicant: Justin Potok Bandholz ,  Thomas Dixon Pahel, Jr. ,  Pravin Patel ,  Philip Louis Weinstein

Inventor： Justin Potok Bandholz ,  Thomas Dixon Pahel, Jr. ,  Pravin Patel ,  Philip Louis Weinstein

IPC: H04B5/00

CPC classification number: G06F13/385 ,  H01R13/665

Abstract: According to one embodiment, an apparatus has first and second connectors configured for removably connecting to one another. The first connector circuit has a first differential amplifier, a first differential signal path, a first capacitor section capacitively coupling the first differential amplifier to the first differential signal path, and a first DC biasing circuit for imparting a first DC bias to the first differential signal path opposite the first capacitor section. The second connector circuit has a second differential amplifier, a second differential signal path, a second capacitor section capacitively coupling the second differential amplifier to the second differential signal path, and a second DC biasing circuit for imparting a second DC bias to the second differential signal path opposite the second capacitor section having a different magnitude than the first DC bias when the first and second connector are not connected. One or both of the first and second connector circuits is configured for detecting a change in the first or second DC bias and outputting a connection status signal in response to the detected change.

Abstract translation: 根据一个实施例，一种装置具有被配置为可互相连接的第一和第二连接件。 第一连接器电路具有第一差分放大器，第一差分信号路径，将第一差分放大器电容耦合到第一差分信号路径的第一电容器部分和用于向第一差分信号施加第一DC偏置的第一DC偏置电路 路径与第一电容器部分相对。 第二连接器电路具有第二差分放大器，第二差分信号路径，将第二差分放大器电容耦合到第二差分信号路径的第二电容器部分，以及用于向第二差分信号施加第二DC偏置的第二DC偏置电路 当所述第一和第二连接器未连接时，所述第二电容器部分的路径与所述第一DC偏置的幅度不同。 第一和第二连接器电路中的一个或两个被配置用于检测第一或第二DC偏置的变化，并且响应于检测到的变化而输出连接状态信号。

公开(公告)号：US08107254B2

公开(公告)日：2012-01-31

申请号：US12274407

申请日：2008-11-20

Applicant: Justin P. Bandholz ,  Jonathan R. Hinkle ,  Pravin Patel

Inventor： Justin P. Bandholz ,  Jonathan R. Hinkle ,  Pravin Patel

IPC: H05K3/00

CPC classification number: H05K1/162 ,  H05K1/0239 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09809

Abstract: A printed circuit board (‘PCB’) with a capacitor integrated within a via of the PCB, the PCB including layers of laminate; a via that includes a via hole traversing layers of the PCB, the via hole characterized by a generally tubular inner surface; a capacitor integrated within the via, the capacitor including two capacitor plates, an inner plate and an outer plate, the two plates composed of electrically conductive material disposed upon the inner surface of the via hole, both plates traversing layers of the laminate, the inner plate traversing more layers of the laminate than are traversed by the outer plate; and a layer of dielectric material disposed between the two plates.

Abstract translation: 印刷电路板（“PCB”），其电容器集成在PCB的通孔内，PCB包括层压板; 通孔，其包括穿过所述PCB的层的通孔，所述通孔的特征在于大致管状的内表面; 集成在通孔内的电容器，电容器包括两个电容器板，内板和外板，两个板由设置在通孔内表面上的导电材料组成，两个板横跨层压板，内部 板穿过层压板比由外板穿过的多层; 以及设置在两个板之间的介电材料层。

公开(公告)号：US08106666B2

公开(公告)日：2012-01-31

申请号：US12402806

申请日：2009-03-12

Applicant: Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

Inventor： Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

IPC: G01R31/02

CPC classification number: G01R31/2806 ,  G01R15/183

Abstract: Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters.

Abstract translation: 测试电气部件，该部件包括具有多个迹线的印刷电路板（“PCB”），该迹线与成对的每个迹线成对地沿着相反的方向承载电流，并且彼此分离由基底层 PCB，其中电气部件的测试包括：动态地和迭代地，直到组件的一对迹线的当前阻抗大于预定阈值阻抗：通过测试装置的阻抗改变装置增加磁场 通过阻抗变化装置施加到该对迹线的磁场的强度，包括增加该对迹线的当前阻抗; 由所述测试装置测量一个或多个操作参数; 并由测试装置记录操作参数的测量值。

公开(公告)号：US20110080973A1

公开(公告)日：2011-04-07

申请号：US12574923

申请日：2009-10-07

Applicant: Rubina F. Ahmed ,  Bradley D. Herrman ,  Pravin Patel ,  Peter R. Seidel

Inventor： Rubina F. Ahmed ,  Bradley D. Herrman ,  Pravin Patel ,  Peter R. Seidel

IPC: H04L27/00 ,  H04B15/00

CPC classification number: H04L25/0274 ,  H04L25/0284

Abstract: Embodiments of the invention include a common mode cancellation circuit and method for correcting signal skew in a differential circuit. According to one embodiment, an op amp circuit is used to correct the mismatch between transmission line lengths in the differential circuit. The CMCC can be embodied as an ASIC and added on to an existing differential signaling systems to correct and compensate for board wiring skew or other causes of phase misalignment. The result is restoration of the cross-over intersection of the plus and minus signals of the differential pair closer to the common voltage level point, as if the signals had been in phase.

Abstract translation: 本发明的实施例包括用于校正差分电路中的信号偏移的共模消除电路和方法。 根据一个实施例，使用运算放大器电路来校正差分电路中的传输线路长度之间的失配。 CMCC可以实现为ASIC，并添加到现有的差分信号系统上，以纠正和补偿电路板布线偏移或相位未对准的其他原因。 结果是恢复差分对的正负信号与公共电压电平点的交叉交叉，好像信号是同相的。

公开(公告)号：US20110066895A1

公开(公告)日：2011-03-17

申请号：US12560088

申请日：2009-09-15

Applicant: David Windell ,  Pravin Patel ,  James Hughes ,  Christopher West ,  Robert Piper ,  Timothy Schlude

Inventor： David Windell ,  Pravin Patel ,  James Hughes ,  Christopher West ,  Robert Piper ,  Timothy Schlude

IPC: G06F11/34

CPC classification number: G06F11/325 ,  H04L41/0645

Abstract: Methods and systems for implementing such methods for providing server fault notifications, diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node.The displaying of the diagnostic service notifications may allow for the completion of various service operations associated with the service notifications once the information specific to a fault is presented. Such service operations may include placing a system in standby mode, transferring workloads to other systems, initiating a firmware update, placing the system in a mode that allows for physical maintenance, or ordering parts associated with one or more faults.

Abstract translation: 用于实现用于提供服务器故障通知，诊断和系统管理信息的这种方法的方法和系统可以包括但不限于：接收网络故障状态请求输入; 为具有一个或多个故障的一个或多个退化服务器节点照亮一个或多个服务器节点故障指示符; 接收具有一个或多个故障的劣化服务器节点的服务器节点故障状态请求输入; 以及显示针对所述退化服务器节点的一个或多个故障的一个或多个诊断服务通知。 一旦出现故障特有的信息，诊断服务通知的显示可以允许完成与服务通知相关联的各种服务操作。 这样的服务操作可以包括将系统置于待机模式，将工作负载传输到其他系统，启动固件更新，将系统置于允许物理维护的模式中，或者订购与一个或多个故障相关联的部件。

公开(公告)号：US20090273911A1

公开(公告)日：2009-11-05

申请号：US12114934

申请日：2008-05-05

Applicant: Justin Potok Bandholz ,  Thomas Dixon Pahel, Jr. ,  Pravin Patel ,  Philip Louis Weinstein

Inventor： Justin Potok Bandholz ,  Thomas Dixon Pahel, Jr. ,  Pravin Patel ,  Philip Louis Weinstein

IPC: H01R9/00 ,  H01R13/60

CPC classification number: G06F13/385 ,  H01R13/665

Abstract: According to one embodiment, an apparatus has first and second connectors configured for removably connecting to one another. The first connector circuit has a first differential amplifier, a first differential signal path, a first capacitor section capacitively coupling the first differential amplifier to the first differential signal path, and a first DC biasing circuit for imparting a first DC bias to the first differential signal path opposite the first capacitor section. The second connector circuit has a second differential amplifier, a second differential signal path, a second capacitor section capacitively coupling the second differential amplifier to the second differential signal path, and a second DC biasing circuit for imparting a second DC bias to the second differential signal path opposite the second capacitor section having a different magnitude than the first DC bias when the first and second connector are not connected. One or both of the first and second connector circuits is configured for detecting a change in the first or second DC bias and outputting a connection status signal in response to the detected change.

Abstract translation: 根据一个实施例，一种装置具有被配置为可互相连接的第一和第二连接件。 第一连接器电路具有第一差分放大器，第一差分信号路径，将第一差分放大器电容耦合到第一差分信号路径的第一电容器部分和用于向第一差分信号施加第一DC偏置的第一DC偏置电路 路径与第一电容器部分相对。 第二连接器电路具有第二差分放大器，第二差分信号路径，将第二差分放大器电容耦合到第二差分信号路径的第二电容器部分，以及用于向第二差分信号施加第二DC偏置的第二DC偏置电路 当所述第一和第二连接器未连接时，所述第二电容器部分的路径与所述第一DC偏置的幅度不同。 第一和第二连接器电路中的一个或两个被配置用于检测第一或第二DC偏置的变化，并且响应于检测到的变化而输出连接状态信号。

公开(公告)号：US20060205703A1

公开(公告)日：2006-09-14

申请号：US11432742

申请日：2006-05-11

Applicant: Pravin Patel

Inventor： Pravin Patel

IPC: A61K31/573 ,  A61K31/22

CPC classification number: A61K31/202 ,  A61K9/0014 ,  A61K31/573 ,  A61K47/44

Abstract: Stabilized, 17-substituted hydrocortisone containing compositions and methods of manufacture are disclosed. Isomerization of the hydrocortisone component of topical steroid compositions is markedly reduced by including an omega-6 acid component in the form of a free acid or as a compound such as an ester. Specifically disclosed are methods for preventing the isomerization of hydrocortisone 17-butyrate into hydrocortisone 21-butyrate through the use of safflower oil.

公开(公告)号：US20060170473A1

公开(公告)日：2006-08-03

申请号：US11344323

申请日：2006-01-31

Applicant: Jim Childers ,  Pravin Patel

Inventor： Jim Childers ,  Pravin Patel

IPC: H03K5/12

CPC classification number: H03K17/6872 ,  H03K17/163 ,  H03K17/165 ,  H03K17/166

Abstract: A method and apparatus independently controls the increasing rate and the decreasing rate a P-channel power FET and an N-channel power FET driving an inductive load. Circuits inhibit turning ON the P-channel FET until the voltage on the gate of the N-channel FET falls below its turn-on voltage threshold, and turning ON the N-channel FET until the voltage on the gate of the P-channel FET falls below its turn-on voltage threshold.

Abstract translation: 一种方法和装置独立地控制P沟道功率FET和驱动感性负载的N沟道功率FET的增加速率和降低速率。 电路禁止接通P沟道FET，直到N沟道FET的栅极上的电压下降到其导通电压阈值以下，并将N沟道FET导通，直到P沟道FET栅极上的电压 低于其导通电压阈值。

公开(公告)号：US4901280A

公开(公告)日：1990-02-13

申请号：US342584

申请日：1989-04-19

Applicant: Pravin Patel

Inventor： Pravin Patel

IPC: G11C11/408

CPC classification number: G11C11/4085

Abstract: A circuit for assisting the charging of a line conductor having a distributed resistance and capacitance, such as a word line in a semiconductor memory device, is disclosed. In the conventional memory device, a driver circuit is disposed at one end of a word line, with a circuit for holding unselected word lines at the discharged voltage being disposed at the end of the word line opposite from the drive circuit. The invention is directed towards a pull-up circuit being disposed at the end of the word line opposite the driver circuit, the pull-up circuit having a transistor which is precharged to a high voltage prior to the active cycle. The precharged transistor is discharged as the selected word line is charged by the driver circuit, causing a driving node in the circuit to be connected to a high supply voltage. The driving node is connected to the word line by a transistor which is responsive to a select signal generated by the address decoder; once selected, the word line at the end opposite the driver circuit is driven by the high supply voltage. This will enable the selected word line to be pulled up to the high supply voltage at both ends, thereby reducing the time required to charge the word line to the required voltage level. The pull-up circuit may also include a transistor for holding the word line low, if unselected; this transistor is made non-conductive as the precharged transistor is discharged. Further disclosed is a circuit which allows a plurality of word lines to share the precharging and driving transistors, but which dedicates for each word line the "bleeder" transistor for holding unselected word lines low and the transistors for coupling the driving node to the word line. In addition, a circuit which provides a reduced voltage at the bleeder transistor, thereby speeding up the charging of the word line by the driver circuit, is disclosed.

Abstract translation: 公开了一种用于辅助对具有分布电阻和电容的线路导体进行充电的电路，例如半导体存储器件中的字线。 在传统的存储器件中，驱动电路设置在字线的一端，用于保持放电电压下的未选字线的电路设置在与驱动电路相反的字线的端部。 本发明涉及一种设置在与驱动器电路相对的字线的端部处的上拉电路，该上拉电路具有在主动周期之前预充电至高电压的晶体管。 当所选字线被驱动电路充电时，预充电晶体管被放电，导致电路中的驱动节点连接到高电源电压。 驱动节点通过响应于由地址解码器产生的选择信号的晶体管连接到字线; 一旦选择，与驱动电路相反的一端的字线由高电源电压驱动。 这将使所选择的字线在两端被拉高到高电源电压，从而减少将字线充电到所需电压电平所需的时间。 上拉电路还可以包括用于将字线保持为低电平的晶体管，如果未被选择的话; 当预充电晶体管放电时，该晶体管是不导通的。 进一步公开的是允许多个字线共享预充电和驱动晶体管但是为每个字线专用用于将未选字线保持为低电平的“泄放”晶体管和用于将驱动节点耦合到字线的晶体管的电路 。 此外，公开了一种在放电晶体管处提供降低的电压，从而加速由驱动器电路对字线进行充电的电路。