公开(公告)号：US20060170473A1

公开(公告)日：2006-08-03

申请号：US11344323

申请日：2006-01-31

Applicant: Jim Childers ,  Pravin Patel

Inventor： Jim Childers ,  Pravin Patel

IPC: H03K5/12

CPC classification number: H03K17/6872 ,  H03K17/163 ,  H03K17/165 ,  H03K17/166

Abstract: A method and apparatus independently controls the increasing rate and the decreasing rate a P-channel power FET and an N-channel power FET driving an inductive load. Circuits inhibit turning ON the P-channel FET until the voltage on the gate of the N-channel FET falls below its turn-on voltage threshold, and turning ON the N-channel FET until the voltage on the gate of the P-channel FET falls below its turn-on voltage threshold.

Abstract translation: 一种方法和装置独立地控制P沟道功率FET和驱动感性负载的N沟道功率FET的增加速率和降低速率。 电路禁止接通P沟道FET，直到N沟道FET的栅极上的电压下降到其导通电压阈值以下，并将N沟道FET导通，直到P沟道FET栅极上的电压 低于其导通电压阈值。

公开(公告)号：US08873249B2

公开(公告)日：2014-10-28

申请号：US13439221

申请日：2012-04-04

Applicant: Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

Inventor： Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

IPC: H05K1/11 ,  G06F1/18

CPC classification number: G06F1/185 ,  Y10T29/49147

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract translation: 一种DIMM转接卡，其包括具有第一边缘，第二边缘和一个或多个面部的PCB。 PCB的第一个边缘被配置为插入主板DIMM插槽。 第一个边缘包括电耦合到存储器总线的电迹线。 DIMM转接卡包括安装在PCB的一个面上的倾斜的DIMM插槽，其中倾斜的DIMM插槽被配置为以不垂直于PCB的角度接受DIMM并将DIMM电耦合到存储器总线。 DIMM转接卡包括安装在PCB第二边缘上的跨骑式DIMM插槽。 跨骑式DIMM插槽被配置为接受DIMM并通过PCB第一边缘上的电迹线将DIMM电连接到存储器总线。

公开(公告)号：US20140102529A1

公开(公告)日：2014-04-17

申请号：US13741070

申请日：2013-01-14

Applicant: Cory Tourino ,  Arthur Cornfeld ,  Pravin Patel ,  Andreea Boca

Inventor： Cory Tourino ,  Arthur Cornfeld ,  Pravin Patel ,  Andreea Boca

IPC: H01L31/02

CPC classification number: H01L31/02008 ,  H01L31/0512 ,  Y02E10/50

Abstract: A solar cell interconnect assembly and a method for manufacturing the same are provided. In an embodiment, the method may include: providing a solar cell having an interconnect member formed thereon, the interconnect member comprising a metallic part formed on a surface of the solar cell and a first precursor layer formed over the metallic part; providing an interconnector comprising a second precursor layer at a surface thereof; heating the interconnector and the interconnect member to a temperature equal to or above a eutectic temperature of the materials of the first and second precursor layers and pressing one of them against the other so as to form a eutectic liquid phase; and isothermal solidifying the eutectic liquid to form a bonding layer of eutectic alloy.

Abstract translation: 提供了一种太阳能电池互连组件及其制造方法。 在一个实施例中，该方法可以包括：提供具有形成在其上的互连构件的太阳能电池，所述互连构件包括形成在太阳能电池的表面上的金属部分和形成在金属部分上的第一前体层; 提供在其表面上包括第二前体层的互连器; 将互连器和互连构件加热到等于或高于第一和第二前体层的材料的共晶温度的温度，并将它们中的一个压在另一个之上以形成共晶液相; 等温固化共晶液体，形成共晶合金的粘结层。

公开(公告)号：US08589741B2

公开(公告)日：2013-11-19

申请号：US13458319

申请日：2012-04-27

Applicant: David Windell ,  Pravin Patel ,  James Hughes ,  Christopher West ,  Robert Piper ,  Timothy Schlude

Inventor： David Windell ,  Pravin Patel ,  James Hughes ,  Christopher West ,  Robert Piper ,  Timothy Schlude

IPC: G06F11/00

CPC classification number: G06F11/325 ,  H04L41/0645

Abstract: Methods and systems for implementing such methods for providing server fault notifications, diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node.The displaying of the diagnostic service notifications may allow for the completion of various service operations associated with the service notifications once the information specific to a fault is presented.

Abstract translation: 用于实现用于提供服务器故障通知，诊断和系统管理信息的这种方法的方法和系统可以包括但不限于：接收网络故障状态请求输入; 为具有一个或多个故障的一个或多个退化服务器节点照亮一个或多个服务器节点故障指示符; 接收具有一个或多个故障的劣化服务器节点的服务器节点故障状态请求输入; 以及显示针对所述退化服务器节点的一个或多个故障的一个或多个诊断服务通知。 一旦出现故障特有的信息，诊断服务通知的显示可以允许完成与服务通知相关联的各种服务操作。

公开(公告)号：US07906950B2

公开(公告)日：2011-03-15

申请号：US12270477

申请日：2008-11-13

Applicant: Justin P. Bandholz ,  Nickolas J. Gruendler ,  Pravin Patel

Inventor： Justin P. Bandholz ,  Nickolas J. Gruendler ,  Pravin Patel

IPC: G05F1/00 ,  G05D17/00

CPC classification number: H02M3/156

Abstract: Tuning a switching power supply, the power supply including a switching transistor; a filter circuit; a pulse generator that drives the switching transistor; a programmable filter connected to the output of the filter circuit; a digital signal processor (‘DSP’) connected to the output of the filter circuit, the DSP configured to program the programmable filter; and a tuning control circuit connected to the output of the filter circuit, to the pulse generator, and to the DSP; including calculating by the DSP, from sampled voltage values of a tuning pulse driven through the filter circuit by the pulse generator, the actual impedance of the filter circuit; and programming, by the DSP, the programmable filter, setting the combined impedance of the filter circuit and the programmable filter to the design impedance of the filter circuit.

Abstract translation: 调谐开关电源，电源包括开关晶体管; 滤波电路; 驱动开关晶体管的脉冲发生器; 连接到滤波电路的输出的可编程滤波器; 数字信号处理器（“DSP”）连接到滤波电路的输出端，DSP配置为对可编程滤波器进行编程; 以及调谐控制电路，连接到滤波电路的输出，脉冲发生器和DSP; 包括由DSP计算的脉冲发生器通过滤波电路驱动的调谐脉冲的采样电压值，滤波器电路的实际阻抗; 并由DSP编程可编程滤波器，将滤波电路和可编程滤波器的组合阻抗设置为滤波电路的设计阻抗。

公开(公告)号：US07725783B2

公开(公告)日：2010-05-25

申请号：US11780505

申请日：2007-07-20

Applicant: Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

Inventor： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

IPC: G11C29/00

CPC classification number: G01R31/2815 ,  G01R31/304 ,  G11C29/02 ,  G11C29/022 ,  G11C29/56 ,  G11C2029/5602

Abstract: The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.

Abstract translation: 本发明通过计算由诸如偶极天线的装置收集的辐射场的频率内容来评估存储器（DIMM）强度。 辐射场由加速电荷产生，这是压摆率或DIMM强度的函数。 辐射功率与驱动位的频率成正比。 通过将辐射场与近场或存储场分离，DIMM强度内容与其他功能性DIMM问题（例如tRCD延迟，刷新周期，寻址模式等）隔离。通过检查辐射功率，现有技术的缺点 ，例如通过探测DIMM的触点。

公开(公告)号：US07704748B2

公开(公告)日：2010-04-27

申请号：US10519313

申请日：2003-06-26

Applicant: Christopher G. Schaeffer ,  Matthew James Schaeffer ,  Pravin Patel

Inventor： Christopher G. Schaeffer ,  Matthew James Schaeffer ,  Pravin Patel

IPC: G01N25/28

CPC classification number: G01N25/36 ,  G01N1/2258 ,  G01N25/28 ,  G01N25/50 ,  Y10T436/218

Abstract: A novel Flame Temperature Analyzer (FTA) method and apparatus for measuring combustible gas concentration and oxygen content in a sample gas includes supplying a mixture of oxidant and fuel to a sensing flame and measuring the temperature of the flame as the sample is added to the combustion chamber.

Abstract translation: 用于测量样品气体中的可燃气体浓度和氧含量的新型火焰温度分析仪（FTA）方法和装置包括将氧化剂和燃料的混合物供应到感测火焰中，并且在将样品加入到燃烧中时测量火焰的温度 房间。

公开(公告)号：US07701222B2

公开(公告)日：2010-04-20

申请号：US11875001

申请日：2007-10-19

Applicant: Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Erdem Matoglu ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Nam Huu Pham ,  Caleb James Wesley

Inventor： Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Erdem Matoglu ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Nam Huu Pham ,  Caleb James Wesley

IPC: G01K3/00 ,  G01J5/00 ,  G01K17/00 ,  G01R27/32

CPC classification number: G01N25/72 ,  G01J5/0096 ,  G01R31/2818 ,  G01R31/2837 ,  G01R31/309

Abstract: A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.

Abstract translation: 一种用于测试印刷电路板以确定与电路板材料相关的介电损耗相对于标准的方法。 当诸如微波频率信号的高频电子信号通过嵌入在印刷电路板内的微带传输时，材料中的介电损耗产生热量。 测量印刷电路板表面的温度或光谱，并与标准品的温度或光谱进行比较，以确定被测材料是否可接受。 尽管可以使用各种温度测量装置，但是优选地在不接触表面的情况下测量温度，例如使用红外辐射探针。

公开(公告)号：US07667980B2

公开(公告)日：2010-02-23

申请号：US11539990

申请日：2006-10-10

Applicant: Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel, Jr. ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

Inventor： Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel, Jr. ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

IPC: H05K7/00

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K3/429 ,  H05K2201/0792 ,  H05K2201/09318 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/1003

Abstract: Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.

Abstract translation: 公开了用于对抗信号失真的印刷电路板，其包括：在发射器和接收器之间的印刷电路板上的导电路径，由连接在一起的迹线和通孔组成的导电通路，用于将信号从发射器传导到接收器; 在印刷电路板上的寄生元件，寄生元件具有扭曲信号的寄生效应; 以及一个或多个无源元件安装在导电路径附近而不连接到导电路径，无源元件具有校正效果，以减少由信号引起的寄生效应的失真。

公开(公告)号：US20080301347A1

公开(公告)日：2008-12-04

申请号：US11756656

申请日：2007-06-01

Applicant: Justin P. Bandholz ,  Robert J. Christopher ,  Joseph M. Jacobs ,  Pravin Patel

Inventor： Justin P. Bandholz ,  Robert J. Christopher ,  Joseph M. Jacobs ,  Pravin Patel

IPC: G06F13/14 ,  H04H7/00

CPC classification number: G06F13/4072

Abstract: A system for allowing a designer to implement Universal Serial Bus (USB) 2.0 in topologies not anticipated by a USB 2.0 specification and with reduced channel losses, the system comprising: a bus channel having a plurality of electrical elements; and a boost circuit connected at a predetermined location on the bus channel; a plurality of USB signals transmitted through the system; wherein edges of the plurality of USB signals are boosted without impacting the bi-directional nature of the bus channel.

Abstract translation: 一种用于允许设计者在USB 2.0规范未预期的拓扑中实现通用串行总线（USB）2.0和减少的信道损失的系统，该系统包括：具有多个电气元件的总线通道; 以及连接在所述总线通道上的预定位置处的升压电路; 通过系统传输的多个USB信号; 其中所述多个USB信号的边缘被提升而不影响所述总线信道的双向性质。