公开(公告)号：US10090040B1

公开(公告)日：2018-10-02

申请号：US15472622

申请日：2017-03-29

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Chun ,  Yanru Li

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: Systems and methods are disclosed for reducing memory power consumption via pre-filled dynamic random access memory (DRAM) values. One embodiment is a method for providing DRAM values. A fill request is received from an executing program to fill an allocated portion of the DRAM with a predetermined pattern of values. The predetermined pattern of values is stored in a fill value memory residing in the DRAM. A fill command is sent to the DRAM. In response to the fill command, a plurality of sense amp latches are connected to the fill value memory to update the corresponding sense amp latch bits with the predetermined pattern of values stored in the fill value memory.

公开(公告)号：US20180260320A1

公开(公告)日：2018-09-13

申请号：US15457899

申请日：2017-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  William Kimberly

IPC: G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/32

CPC classification number: G06F12/0246 ,  G06F1/3221 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/5016 ,  G06F9/5094 ,  G06F13/1673 ,  G06F13/4068 ,  G06F2212/7201 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/22

Abstract: Systems, methods, and computer programs are disclosed for providing power-efficient file system operation to a non-volatile block memory. An exemplary embodiment of a system comprises a non-volatile block memory having a file system, a dynamic random access memory (DRAM), and a system on chip (SoC). The SoC comprises a central processing unit (CPU), one or more non-core processors, a DRAM controller, a data interface coupled to an off-chip processor, and a multi-host storage controller. The CPU allocates a storage buffer in the non-volatile block memory. The multi-host storage controller comprises a virtualized client interface for providing the non-core and off-chip processors with direct read/write file system access using the allocated storage buffer while the CPU and the DRAM are in a low power state.

公开(公告)号：US20180197594A1

公开(公告)日：2018-07-12

申请号：US15400507

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  Jungwon Suh

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4091

CPC classification number: G11C11/408 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/4091

Abstract: Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.

公开(公告)号：US09779798B1

公开(公告)日：2017-10-03

申请号：US15400515

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  Jungwon Suh ,  Alexander Gantman

IPC: G11C7/00 ,  G11C11/4078 ,  G11C11/406

CPC classification number: G11C8/12 ,  G11C7/1063 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/4087

Abstract: Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

公开(公告)号：US09336855B2

公开(公告)日：2016-05-10

申请号：US13893670

申请日：2013-05-14

Applicant: QUALCOMM Incorporated

Inventor： Haw-Jing Lo ,  Dexter Chun

IPC: G11C7/04 ,  G11C11/406 ,  G11C11/4072

CPC classification number: G11C11/40622 ,  G11C7/04 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40626 ,  G11C11/4072

Abstract: Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT−PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred.

Abstract translation: 用于刷新动态存储设备（例如，DRAM）以消除不必要的页面刷新操作的方法和设备。 该页面的查找表中的值可以指示页面中是否存在包括全部零的有效数据。 当页面包括全零的有效数据时，可以设置查找表值，使得可以禁止页面的刷新，存储器读取，写入和清除访问，并且可以返回有效值。 第二查找表可以包含指示在页面刷新间隔期间页面是否被页面读取或写入访问的第二值。 当第二个值指示没有发生页面访问时，可以根据页面刷新间隔来执行通过发出ACT-PRE命令对的页面刷新和页面地址。