公开(公告)号：US20170038814A1

公开(公告)日：2017-02-09

申请号：US14817178

申请日：2015-08-03

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan Pal

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/3243 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152

Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In one embodiment, a method for activating one or more processors comprises reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors. The method also comprises activating the one or more processors after the frequency of the clock signal is reduced, and increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated.

Abstract translation: 提供了配电网络（PDN）下垂/过冲缓解的系统和方法。 在一个实施例中，用于激活一个或多个处理器的方法包括将时钟信号的频率从第一时钟频率降低到第二时钟频率，其中时钟信号被输出到包括一个或多个处理器的多个处理器。 该方法还包括在时钟信号的频率减小之后激活一个或多个处理器，以及在一个或多个处理器被激活之后将时钟信号从第二时钟频率增加到第一时钟频率。

公开(公告)号：US09564877B2

公开(公告)日：2017-02-07

申请号：US14251297

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan Pal ,  Paul Ivan Penzes ,  Wai Kit Siu

IPC: G01R31/28 ,  H03K3/012 ,  H03K3/037 ,  G11C19/34 ,  G01R31/3185

CPC classification number: H03K3/012 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318594 ,  G11C19/34 ,  H03K3/0375

Abstract: A first apparatus includes at least one scan chain. Each of the at least one scan chain includes scan cells coupled together. Each scan cell in the at least one scan chain includes a first type of scan cell when a reset state of the scan cell is a first state, and a second type of scan cell when the reset state of the scan cell is a second state. One or more scan chains of the at least one scan chain includes at least one of the first type of scan cell and at least one of the second type of scan cell. A second apparatus includes first and second sets of scan chains including flip-flops without both set and reset functionality. Each of the flip-flops in the first and second sets of scan chains has a reset state of a first state and a second state, respectively.

Abstract translation: 第一装置包括至少一个扫描链。 所述至少一个扫描链中的每一个包括耦合在一起的扫描单元。 当扫描单元的复位状态是第一状态时，至少一个扫描链中的每个扫描单元包括第一类型的扫描单元，当扫描单元的复位状态是第二状态时，包括第二类型的扫描单元。 所述至少一个扫描链的一个或多个扫描链包括所述第一类型的扫描单元和所述第二类型的扫描单元中的至少一个。 第二装置包括第一和第二组扫描链，包括没有设置和复位功能的触发器。 第一组扫描链和第二组扫描链中的每个触发器分别具有第一状态和第二状态的复位状态。

公开(公告)号：US09337820B1

公开(公告)日：2016-05-10

申请号：US14629460

申请日：2015-02-23

Applicant: QUALCOMM Incorporated

Inventor： Shahin Solki ,  Dipti Ranjan Pal ,  Paul Ivan Penzes

IPC: H03L7/00 ,  H03K5/156 ,  H03K5/15

CPC classification number: H03K5/1565 ,  H03K5/1504

Abstract: A duty cycle adjustment apparatus includes a duty cycle adjustment determination module configured to determine an adjustment to a duty cycle of a clock signal, and includes a clock delay module configured to receive the clock signal, to delay the clock signal through first and second delay stage modules (with a first and a second plurality of delay paths, respectively) based on the duty cycle adjustment determined by the duty cycle adjustment determination module, and to output the delayed clock signal. The second plurality of delay paths have a greater delay difference between each of the corresponding delay paths than the first plurality of delay paths. The apparatus further includes a duty cycle adjustment module configured to receive the clock signal and the delayed clock signal, to adjust the duty cycle of the clock signal based on the delayed clock signal, and to output a duty cycle adjusted clock signal.

Abstract translation: 占空比调整装置包括占空比调整确定模块，其被配置为确定对时钟信号的占空比的调整，并且包括被配置为接收时钟信号的时钟延迟模块，以通过第一和第二延迟级延迟时钟信号 模块（分别具有第一和第二多个延迟路径），基于由占空比调整确定模块确定的占空比调整，并输出延迟的时钟信号。 第二多个延迟路径在每个相应的延迟路径之间具有比第一多个延迟路径更大的延迟差。 该装置还包括一个占空比调整模块，配置成接收时钟信号和延迟的时钟信号，以便根据延迟的时钟信号来调整时钟信号的占空比，并输出占空比调整后的时钟信号。