公开(公告)号：US20160072480A1

公开(公告)日：2016-03-10

申请号：US14482403

申请日：2014-09-10

申请人： QUALCOMM Incorporated

发明人： Ryan Michael Coutts ,  Wai Kit Siu ,  Paul Ivan Penzes

IPC分类号： H03K3/012 ,  G05B19/045 ,  H03K17/22 ,  H03K3/037

CPC分类号： H03K3/012 ,  G05B19/045 ,  H03K3/0372 ,  H03K17/223 ,  H03K19/0008

摘要： Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are “SET” flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are “RESET” flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

摘要翻译： 提供了减少泄漏的电路和方法。 在一个示例中，系统包括将特定逻辑电路复位到减少泄漏的状态的电路。 对于逻辑电路，预先知道减少泄漏的状态。 在该示例中，逻辑电路包括组合逻辑以及将状态输出到组合逻辑的触发器。 一些触发器是“SET”触发器（当复位输入被置位时，假定为1个输出值），并且一些触发器是“RESET”触发器（假设复位输入被置位时为0）。 触发器被选择为组合逻辑的输入，使得零和一个输出到组合逻辑的特定组合将逻辑电路置于与期望的泄漏水平相关联的状态。

公开(公告)号：US09496851B2

公开(公告)日：2016-11-15

申请号：US14482403

申请日：2014-09-10

申请人： QUALCOMM Incorporated

发明人： Ryan Michael Coutts ,  Wai Kit Siu ,  Paul Ivan Penzes

IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K17/22 ,  H03K19/00 ,  G05B19/045

CPC分类号： H03K3/012 ,  G05B19/045 ,  H03K3/0372 ,  H03K17/223 ,  H03K19/0008

摘要： Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are “SET” flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are “RESET” flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

摘要翻译： 提供了减少泄漏的电路和方法。 在一个示例中，系统包括将特定逻辑电路复位到减少泄漏的状态的电路。 对于逻辑电路，预先知道减少泄漏的状态。 在该示例中，逻辑电路包括组合逻辑以及将状态输出到组合逻辑的触发器。 一些触发器是“SET”触发器（当复位输入被置位时，假定为1个输出值），并且一些触发器是“RESET”触发器（假设复位输入被置位时为0）。 触发器被选择为组合逻辑的输入，使得零和一个输出到组合逻辑的特定组合将逻辑电路置于与期望的泄漏水平相关联的状态。

公开(公告)号：US09564877B2

公开(公告)日：2017-02-07

申请号：US14251297

申请日：2014-04-11

申请人： QUALCOMM Incorporated

发明人： Dipti Ranjan Pal ,  Paul Ivan Penzes ,  Wai Kit Siu

IPC分类号： G01R31/28 ,  H03K3/012 ,  H03K3/037 ,  G11C19/34 ,  G01R31/3185

CPC分类号： H03K3/012 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318594 ,  G11C19/34 ,  H03K3/0375

摘要： A first apparatus includes at least one scan chain. Each of the at least one scan chain includes scan cells coupled together. Each scan cell in the at least one scan chain includes a first type of scan cell when a reset state of the scan cell is a first state, and a second type of scan cell when the reset state of the scan cell is a second state. One or more scan chains of the at least one scan chain includes at least one of the first type of scan cell and at least one of the second type of scan cell. A second apparatus includes first and second sets of scan chains including flip-flops without both set and reset functionality. Each of the flip-flops in the first and second sets of scan chains has a reset state of a first state and a second state, respectively.

摘要翻译： 第一装置包括至少一个扫描链。 所述至少一个扫描链中的每一个包括耦合在一起的扫描单元。 当扫描单元的复位状态是第一状态时，至少一个扫描链中的每个扫描单元包括第一类型的扫描单元，当扫描单元的复位状态是第二状态时，包括第二类型的扫描单元。 所述至少一个扫描链的一个或多个扫描链包括所述第一类型的扫描单元和所述第二类型的扫描单元中的至少一个。 第二装置包括第一和第二组扫描链，包括没有设置和复位功能的触发器。 第一组扫描链和第二组扫描链中的每个触发器分别具有第一状态和第二状态的复位状态。

公开(公告)号：US20150356229A1

公开(公告)日：2015-12-10

申请号：US14300000

申请日：2014-06-09

申请人： QUALCOMM Incorporated

发明人： Wai Kit Siu ,  Paul Ivan Penzes

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G01R31/2858 ,  G06F17/5036 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

摘要： Systems and methods for efficiently generating electromigration reliability data for physical cells in an integrated circuit cell library are disclosed. Data for tables of electromigration susceptibility can be iteratively generated for multiple capacitive loadings on a cell output and for multiple transition times of a cell input. Each iteration can include simulating electrical performance of the physical cell and identifying a region with the largest ratio of current density to electromigration reliability limit. Between iterations, the data period of the input signal is updated using the ratio of current density to electromigration reliability limit and a relationship between currents and data period. Iterations may end when the ratio is close to one. The result can be used to evaluate electromigration reliability of an integrated circuit design and modify the design accordingly.

摘要翻译： 公开了用于有效地生成集成电路单元库中物理单元的电迁移可靠性数据的系统和方法。 可以迭代地产生用于电池输出上的多个电容负载和电池输入的多个转换时间的电迁移敏感性表的数据。 每个迭代可以包括模拟物理单元的电气性能，并确定具有最大电流密度比与电迁移可靠性限制的区域。 在迭代之间，使用电流密度与电迁移可靠性限制的比率以及电流和数据周期之间的关系来更新输入信号的数据周期。 当比率接近1时，迭代可能会结束。 结果可用于评估集成电路设计的电迁移可靠性，并相应地修改设计。