公开(公告)号：US20220013522A1

公开(公告)日：2022-01-13

申请号：US16924757

申请日：2020-07-09

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Haining YANG

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8234

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with buried rails (e.g., buried power and ground rails). One example semiconductor device generally includes a substrate; a first rail, wherein a portion of the first rail is disposed in the substrate, the portion of the first rail having a first width greater than a second width of another portion of the first rail; a second rail, wherein a portion of the second rail is disposed in the substrate, the portion of the second rail having a third width greater than a fourth width of another portion of the second rail; and one or more transistors disposed above the substrate and between the first rail and the second rail.

公开(公告)号：US20210398972A1

公开(公告)日：2021-12-23

申请号：US16908126

申请日：2020-06-22

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Haining YANG ,  Xia LI ,  Kwanyong LIM

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/737 ,  H01L29/786 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/08

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a heterojunction bipolar transistor (HBT) integrated with a gate-all-around (GAA) transistor. One example semiconductor device generally includes a first substrate, a second substrate adjacent to the first substrate, a GAA transistor disposed above the first substrate, and a HBT disposed above the second substrate. Other aspects of the present disclosure generally relate to a method for fabricating a semiconductor device. An exemplary fabrication method generally comprises forming a GAA transistor disposed above a first substrate and forming a HBT disposed above a second substrate, wherein the second substrate is adjacent to the first substrate.

公开(公告)号：US20210036120A1

公开(公告)日：2021-02-04

申请号：US16526756

申请日：2019-07-30

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Haining YANG ,  Xia LI

IPC: H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

公开(公告)号：US20170236815A1

公开(公告)日：2017-08-17

申请号：US15582770

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang LIU ,  Haining YANG

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

公开(公告)号：US20250133772A1

公开(公告)日：2025-04-24

申请号：US18493634

申请日：2023-10-24

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong LIM ,  Hyunwoo PARK ,  Junjing BAO ,  Chih-Sung YANG ,  Ming-Huei LIN ,  Haining YANG

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A gate all around (GAA) field effect transistor (GAA FET) is described. The GAA FET includes a substrate, having a nanosheet structure on the substrate. The GAA FET also includes a source/drain (SD) region in the substrate and coupled to a first end of the nanosheet structure. The GAA FET further includes a drain/source (DS) region in the substrate and coupled to a second end opposite the first end of the nanosheet structure. The GAA FET also includes a metal gate on the nanosheet structure to define channels between the source/drain region and the drain/source region. The GAA FET further includes a trench oxide blocking a bottom channel of the channels.

公开(公告)号：US20240421214A1

公开(公告)日：2024-12-19

申请号：US18334301

申请日：2023-06-13

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Kwanyong LIM ,  Haining YANG ,  Biswa Ranjan PANDA ,  Ramesh MANCHANA

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A field effect transistor (FET) is described. The FET includes a substrate, having a first vertical structure on the substrate, including a source/drain region having a first stressor material. The FET also includes a second vertical structure on the substrate and including a drain/source region having a second stressor material different from the first stressor material. The FET further includes a metal gate on the first vertical structure and on the second vertical structure.

公开(公告)号：US20220293513A1

公开(公告)日：2022-09-15

申请号：US17198941

申请日：2021-03-11

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Haining YANG

IPC: H01L23/522 ,  H01L21/8234 ,  H02J50/05 ,  H01L27/06 ,  H01L49/02 ,  H01L23/528

Abstract: Disclosed are examples of a device including a front side metallization portion having a front side BEOL. The device also includes a backside BEOL. The device also includes a substrate, where the substrate is disposed between the backside BEOL and the front side metallization portion. The device also includes a metal-insulator-metal (MIM) capacitor embedded in the backside BEOL.

公开(公告)号：US20220123101A1

公开(公告)日：2022-04-21

申请号：US17074026

申请日：2020-10-19

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Jun YUAN ,  Haining YANG ,  Bin YANG

IPC: H01L49/02 ,  H01L23/522

Abstract: Disclosed are examples of 3D metal-insulator-metal (MIM) capacitor structures, e.g., in semiconductor packages. The disclosed 3D MIM capacitors provide high capacitance in small areas. As such, the disclosed 3D MIM capacitors may be used as decoupling capacities for high performance computing (HPC) processors.

公开(公告)号：US20210359108A1

公开(公告)日：2021-11-18

申请号：US16875668

申请日：2020-05-15

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Xia LI ,  Bin YANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having an insulator region disposed on at least one edge of a semiconductor fin structure. An example semiconductor device generally includes a first semiconductor region, an insulator region, a double diffusion break, and a first gate region. The first semiconductor region comprises a first fin structure and a second fin structure separated by a cavity. The insulator region is disposed along an edge of the first fin structure. The double diffusion break is disposed adjacent to the insulator region in the cavity. The first gate region is disposed around a portion of the first fin structure.

公开(公告)号：US20210280722A1

公开(公告)日：2021-09-09

申请号：US16809534

申请日：2020-03-04

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Bin YANG ,  Xia LI

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66

Abstract: Strained silicon transistor, such as GAA transistors, allow for both good PMOS mobility and NMOS mobility on the same substrate. In one example, a GAA circuit may include a NMOS device on a tensile strained Si channel and a PMOS device on a compressive strained SiGe channel. In another example, a GAA circuit may include a NMOS device on a strained Si channel and a PMOS device on a relaxed SiGe channel on (110) crystalline substrate.