公开(公告)号：US09300295B1

公开(公告)日：2016-03-29

申请号：US14626920

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Yaojun Zhang ,  Wenqing Wu ,  Kendrick Hoy Leong Yuen ,  Karim Arabi

IPC: H03K19/18 ,  H03K19/20 ,  H03K19/003

CPC classification number: H03K19/00346 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/22 ,  H01L43/08 ,  H03K3/45 ,  H03K19/18

Abstract: Systems and methods pertain to avoiding undesirable current paths or sneak paths in spintronic logic gates formed from Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) elements. Sneak path prevention logic is coupled to the GSHE MTJ elements, to prevent the sneak paths. The sneak path prevention logic may include one or more transistors coupled to the one or more GSHE MTJ elements, to restrict write current from flowing from an intended pipeline stage to an unintended pipeline stage during a write operation. The sneak path prevention logic may also include one or more diodes coupled to the one or more GSHE MTJ elements to prevent a preset current from flowing into input circuitry or a charge current generation circuit. A preset line may be coupled to the one or more GSHE MTJ elements to divert preset current from flowing into unintended paths.

Abstract translation: 系统和方法涉及避免由巨型旋转霍尔效应（GSHE）磁性隧道结（MTJ）元件形成的自旋电子逻辑门中的不必要的电流路径或潜行路径。 潜行路径预防逻辑耦合到GSHE MTJ元素，以防止潜行路径。 潜行路径预防逻辑可以包括耦合到一个或多个GSHE MTJ元件的一个或多个晶体管，以在写入操作期间限制写入电流从预期流水线级流到非预期流水线级。 潜行路径预防逻辑还可以包括耦合到一个或多个GSHE MTJ元件的一个或多个二极管，以防止预设电流流入输入电路或充电电流产生电路。 预设线可以耦合到一个或多个GSHE MTJ元件，以将预设电流从流入非预期路径转移。

公开(公告)号：US20150323959A1

公开(公告)日：2015-11-12

申请号：US14273833

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Karim Arabi

IPC: G06F1/10

CPC classification number: G06F1/10 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814

Abstract: Clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary aspect, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary aspect, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously.

Abstract translation: 公开了时钟偏斜管理系统。 还公开了方法和相关组件。 在示例性方面，为了抵消可能在时钟树中的层次之间产生的偏斜，跨层时钟平衡方案​​利用自动延迟调整。 特别地，延迟感测电路检测不同层之间的时钟树中可比较点的延迟差异，并且指示可编程延迟元件在两个层级中更快地延迟时钟信号。 在第二示例性方面，将金属网格提供给时钟树中的所有元件，并且充当信号聚合器，其基本同时向时钟元件提供时钟信号。

公开(公告)号：US20140181771A1

公开(公告)日：2014-06-26

申请号：US13725976

申请日：2012-12-21

Applicant: QUALCOMM INCORPORATED

Inventor： Khusro Sajid ,  Mamta Bansal ,  Karim Arabi

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036

Abstract: Methods and apparatus for Enhanced Static IR Drop Analysis are provided. Enhanced Static IR Drop Analysis can be used to determine a quality and robustness of a power distribution network in a circuit. In examples, Enhanced Static IR Drop Analysis includes recording time points at which global current demand profile peaks, sampling instantaneous current from individual tile-based current demand profiles at each time point, and running Static IR Analysis for the tiles at the time points to determine tile current use by the tiles during the time points. Enhanced Static IR Drop Analysis can be used for quick assessment of peak current distribution and determining how the peak current distribution stresses the power distribution network. Enhanced Static IR Drop Analysis is useful during earlier stages of circuit design, when quickly producing circuit performance data is imperative and conventional techniques require significant resources.

Abstract translation: 提供了增强型静态IR滴分析的方法和装置。 增强型静态红外线掉电分析可用于确定电路中配电网络的质量和鲁棒性。 在示例中，增强型静态红外线掉电分析包括记录全局电流需求曲线峰值的时间点，在每个时间点从基于瓦片的当前需求曲线采集瞬时电流，以及在时间点运行瓦片的静态IR分析，以确定 瓦片当前使用的瓦片在时间点。 增强型静态IR降落分析可用于快速评估峰值电流分布，并确定峰值电流分布如何强调配电网络。 在电路设计的早期阶段，当快速生成电路性能数据是必不可少的并且常规技术需要大量资源时，增强型静态IR分析分析是非常有用的。

公开(公告)号：US20130241593A1

公开(公告)日：2013-09-19

申请号：US13887517

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Rajamani Sethuram ,  Karim Arabi

IPC: H03K19/00 ,  G06F17/50 ,  H03K19/173

CPC classification number: H03K19/0008 ,  G01R31/318342 ,  G01R31/318575 ,  G06F17/50 ,  H03K19/173

Abstract: Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.

Abstract translation: 通过确定电路设计的最小泄漏状态，然后选择将电路设计保持在其最低泄漏状态的逻辑门来选择用于Q门控的特定逻辑门。 根据实现最小泄漏状态所需的输入，栅极可以选择为NOR或或门。 在选择的操作模式期间可以启用用于实现最小泄漏状态的门实现的Q门控。 电路的最小泄漏状态可以用自动测试图形生成（ATPG）工具来确定。