公开(公告)号：US20240373560A1

公开(公告)日：2024-11-07

申请号：US18310277

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Seongryul CHOI ,  Kuiwon KANG ,  Hong Bok WE ,  Jung Won PARK

IPC: H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: In an aspect, a substrate is disclosed that includes an electronic component including a lower planar surface having one or more electronic component terminals, a core having an upper planar surface facing the lower planar surface of the electronic component; a patterned metallization layer over the upper planar surface of the core, wherein the patterned metallization layer is connected to the one or more electronic component terminals at the lower planar surface of the electronic component; one or more dielectric layers disposed over the upper planar surface of the core; and a cavity formed within the one or more dielectric layers, wherein the electronic component is located in the cavity and over the upper planar surface of the core.

公开(公告)号：US20230073823A1

公开(公告)日：2023-03-09

申请号：US17471061

申请日：2021-09-09

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Kuiwon KANG ,  Joan Rey Villarba BUOT

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes a core layer comprising a first surface and a second surface; at least one first dielectric layer coupled to the first surface of the core layer; at least one second dielectric layer coupled to the second surface of the core layer; at least one core interconnect that extends through the core layer and at least one dielectric layer from the at least first dielectric layer and/or the at least one second dielectric layer; a plurality of high-density interconnects comprising a first minimum width and a first minimum spacing; and a plurality of interconnects comprising a second minimum width and a second minimum spacing. The second minimum width is greater than the first minimum width. The second minimum spacing is greater than the first minimum spacing.

公开(公告)号：US20220108918A1

公开(公告)日：2022-04-07

申请号：US17064471

申请日：2020-10-06

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Joan Rey Villarba BUOT ,  Jialing TONG

IPC: H01L21/768 ,  H01L21/3213 ,  C25D3/56 ,  H01L23/528 ,  H01L23/00

Abstract: A method of forming electrical interconnections comprises patterning a trace on a dielectric layer and then masking the dielectric layer for plating. The dielectric layer is plated to form electrical interconnections. After plating the masking is removed. A laser etch back of the trace is performed after removing the masking, in which the laser etch back removes tails on the trace. After the laser etch back, the patterned traces and the dielectric layer are cleaned.

公开(公告)号：US20220102298A1

公开(公告)日：2022-03-31

申请号：US17038124

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Michelle Yejin KIM ,  Marcus HSU

IPC: H01L23/00

Abstract: Aspects disclosed herein include a device including a bump pad structure and methods for fabricating the same. The device includes a bump pad. The device also includes a first trace adjacent the bump pad, where a first trace top surface is recessed a first recess distance from a bump pad top surface. The device also includes a second trace adjacent the first trace, covered at least in part by a solder resist. The device also includes a substrate, where the bump pad, the first trace, and the second trace are each formed on a portion of the substrate.

公开(公告)号：US20220077069A1

公开(公告)日：2022-03-10

申请号：US17017418

申请日：2020-09-10

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Kuiwon KANG

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/00

Abstract: A package that includes a substrate and an integrated device. The substrate includes a core portion, a first substrate portion and a second substrate portion. The core portion includes a core layer and core interconnects. The first substrate portion is coupled to the core portion. The first substrate portion includes at least one first dielectric layer coupled to the core layer, and a first plurality of interconnects located in the at least one first dielectric layer. The second substrate portion is coupled to the core portion. The second substrate includes at least one second dielectric layer coupled to the core layer, and a second plurality of interconnects located in the at least one second dielectric layer. The core portion and the second substrate portion include a cavity. The integrated device is coupled to the first substrate portion through the cavity of the second substrate portion and the core portion.

公开(公告)号：US20210407918A1

公开(公告)日：2021-12-30

申请号：US16913288

申请日：2020-06-26

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Brigham NAVAJA ,  Marcus HSU ,  Terence CHEUNG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/522 ,  H01L49/02 ,  H01L21/48 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

公开(公告)号：US20210375736A1

公开(公告)日：2021-12-02

申请号：US17332962

申请日：2021-05-27

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Zhijie WANG ,  Aniket PATIL ,  Hong Bok WE ,  Kuiwon KANG

IPC: H01L23/498 ,  H01L21/48

Abstract: Various package configurations and methods of fabricating the same are disclosed. In some aspects, a package may include a core layer and a first layer directly attached to a first side of the core layer, where a first device is embedded in the first layer. A second layer can be directly attached to a second side of the core layer opposite the first side, where a second passive device is embedded in the second layer. A first build-up layer can be directly attached to the first layer opposite the core layer, and a second build-up layer can be directly attached to the second layer opposite the core layer.

公开(公告)号：US20200020624A1

公开(公告)日：2020-01-16

申请号：US16030936

申请日：2018-07-10

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Joan Rey Villarba BUOT ,  Soumyadipta BASU ,  Charles David PAYNTER

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: A chip package substrate and methods for fabricating the chip package substrate. An exemplary chip package substrate generally includes a first substrate and a second substrate embedded in the first substrate and having a plurality of layered traces embedded therein.

公开(公告)号：US20180350630A1

公开(公告)日：2018-12-06

申请号：US15814355

申请日：2017-11-15

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Marcus HSU ,  Hong Bok WE

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/532 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49822 ,  H01L23/49827

Abstract: Exemplary packages according to some aspects of the disclosure may include a symmetric structure with a thick core for embedded trace substrates. The packages may include an embedded third dielectric layer for preventing bump shorts or trace peel off between fine bump areas with a solder resist trench. This may allow fine bump pitches with escape lines (traces) on flip chip bump array (FCBGA) applications, for example.

公开(公告)号：US20250079348A1

公开(公告)日：2025-03-06

申请号：US18458650

申请日：2023-08-30

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Hong Bok WE ,  Michelle Yejin KIM

IPC: H01L23/64 ,  H01L21/768 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498

Abstract: A substrate comprising: a core layer comprising a cavity; an embedded passive device located at least partially in the cavity of the core layer, wherein the embedded passive device comprises a plurality of pad interconnects; a polyimide layer coupled to a surface of the embedded passive device; at least one dielectric layer coupled to the core layer; and a plurality of interconnects located at least partially in the at least one dielectric layer.