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公开(公告)号：US11922066B2
公开(公告)日：2024-03-05
申请号：US17576529
申请日：2022-01-14
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Michael Raymond Miller , Steven C. Woo
CPC classification number: G06F3/0659 , G06F3/0626 , G06F3/0658 , G06F3/0673 , G11C7/1006
Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.
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公开(公告)号：US20230087576A1
公开(公告)日：2023-03-23
申请号：US17940956
申请日：2022-09-08
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Dongyun Lee
IPC: G06F3/06
Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.
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公开(公告)号：US20220179556A1
公开(公告)日：2022-06-09
申请号：US17544584
申请日：2021-12-07
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Steven C. Woo , Thomas Vogelsang
IPC: G06F3/06
Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.
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公开(公告)号：US20240354014A1
公开(公告)日：2024-10-24
申请号：US18655510
申请日：2024-05-06
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Steven C. Woo , Michael Raymond Miller
IPC: G06F3/06
CPC classification number: G06F3/0634 , G06F3/061 , G06F3/0673
Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.
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公开(公告)号：US20240295961A1
公开(公告)日：2024-09-05
申请号：US18598323
申请日：2024-03-07
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Steven C. Woo , Thomas Vogelsang
IPC: G06F3/06 , G11C11/406
CPC classification number: G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/40611 , G11C11/40615
Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.
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Patent Agency Ranking
公开(公告)号：US12073111B2
公开(公告)日：2024-08-27
申请号：US17940956
申请日：2022-09-08
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Dongyun Lee
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673
Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.
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公开(公告)号：US11934654B2
公开(公告)日：2024-03-19
申请号：US17544584
申请日：2021-12-07
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Steven C. Woo , Thomas Vogelsang
IPC: G06F3/06 , G11C11/406
CPC classification number: G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/40611 , G11C11/40615
Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.
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公开(公告)号：US20230401311A1
公开(公告)日：2023-12-14
申请号：US18202517
申请日：2023-05-26
Applicant: Rambus Inc.
Inventor： Evan Lawrence Erickson , Helena Handschuh , Michael Alexander Hamburg , Mark Evan Marson , Michael Raymond Miller
CPC classification number: G06F21/552 , G06F11/10
Abstract: Technologies for detecting an error using a message authentication code (MAC) associated with cache line data and differentiating the error as having been caused by an attack on memory or a MAC verification failure caused by an ECC escape. One memory buffer device includes an in-line memory encryption (IME) circuit to generate the MACs and verify the MACs. Upon a MAC verification failure, the memory buffer device can analyze at least one of the historical MAC verification failures or historical ECC-corrected errors over time to determine if the error is caused by an attack on memory.
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公开(公告)号：US11645152B2
公开(公告)日：2023-05-09
申请号：US17734464
申请日：2022-05-02
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Stephen Magee , John Eric Linstadt
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0625 , G06F3/0644 , G06F3/0673 , G06F11/1048
Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.
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公开(公告)号：US20230138817A1
公开(公告)日：2023-05-04
申请号：US17971964
申请日：2022-10-24
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Evan Lawrence Erickson
Abstract: A multi-processor device is disclosed. The multi-processor device includes interface circuitry to receive requests from at least one host device. A primary processor is coupled to the interface circuitry to process the requests in the absence of a failure event associated with the primary processor. A secondary processor processes operations on behalf of the primary processor and selectively receives the requests from the interface circuitry based on detection of the failure event associated with the primary processor.
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