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    Supporting calibration for sub-rate operation in clocked memory systems
    21.
    发明授权
    Supporting calibration for sub-rate operation in clocked memory systems 有权
    支持定时存储器系统中子速率操作的校准

    公开(公告)号：US09349422B2

    公开(公告)日：2016-05-24

    申请号：US14687739

    申请日：2015-04-15

    Applicant: Rambus Inc.

    Inventor： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

    IPC: G11C7/22 ,  G11C29/02 ,  G06F1/10

    CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ⅛ of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

    Abstract translation: 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算与子速率频率（例如，全速率频率的1/2，¼或⅛）相关联的子速率校准状态。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

    TIMING-DRIFT CALIBRATION
    23.
    发明申请
    TIMING-DRIFT CALIBRATION 有权

    公开(公告)号：US20220223224A1

    公开(公告)日：2022-07-14

    申请号：US17556363

    申请日：2021-12-20

    Applicant: Rambus Inc.

    Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

    IPC: G11C29/50 ,  G06F13/16 ,  G01R23/02 ,  G11C7/22 ,  G11C29/02 ,  H03L1/02 ,  G11C8/18

    Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

    TIMING-DRIFT CALIBRATION
    25.
    发明申请
    TIMING-DRIFT CALIBRATION 审中-公开

    公开(公告)号：US20200312422A1

    公开(公告)日：2020-10-01

    申请号：US16824005

    申请日：2020-03-19

    Applicant: Rambus Inc.

    Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

    IPC: G11C29/50 ,  G06F13/16 ,  G01R23/02 ,  G11C7/22 ,  G11C29/02 ,  H03L1/02 ,  G11C8/18

    Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

    Timing-drift calibration
    27.
    发明授权
    Timing-drift calibration 有权
    定时漂移校准

    公开(公告)号：US09362006B2

    公开(公告)日：2016-06-07

    申请号：US14570773

    申请日：2014-12-15

    Applicant: RAMBUS INC.

    Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

    IPC: G06F1/04 ,  G01R23/00 ,  G01R23/10 ,  G01D21/00 ,  G01R35/00 ,  G11C29/50 ,  G06F13/16 ,  G01R23/02 ,  G11C7/22 ,  G11C29/02 ,  H03L1/02 ,  G11C8/18 ,  G06F11/16 ,  G06F1/12 ,  G06F1/08 ,  G01R23/15 ,  G11C7/04

    CPC classification number: G11C29/50012 ,  G01R23/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L1/02

    Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.

    Abstract translation: 所公开的实施例涉及支持定时漂移校准的存储器系统的组件。 在具体实施例中，该存储器系统包含存储器件（或多个器件），其包括可产生频率的时钟分配电路和振荡器电路，其中频率变化表示时钟分配电路的定时漂移。 存储装置还包括被配置为测量振荡器电路的频率的测量电路。 此外，存储器系统包含存储器控制器，该存储器控制器可向存储器件发送请求以触发存储器件以测量振荡器电路的频率。 存储器控制器还被配置为从存储器件接收测量的频率，并使用测量的频率来确定存储器件中的定时漂移。

    Supporting Calibration For Sub-Rate Operation In Clocked Memory Systems
    29.
    发明申请
    Supporting Calibration For Sub-Rate Operation In Clocked Memory Systems 有权
    支持时钟存储系统中子速率操作的校准

    公开(公告)号：US20150310903A1

    公开(公告)日：2015-10-29

    申请号：US14687739

    申请日：2015-04-15

    Applicant: Rambus Inc.

    Inventor： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

    IPC: G11C7/22

    CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

    Abstract translation: 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2，1/4或1/8）相关联 频率）。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

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