公开(公告)号：US20160029021A1

公开(公告)日：2016-01-28

申请号：US14752883

申请日：2015-06-27

Applicant: Renesas Electronics Corporation

Inventor： Kenichi IWATA ,  Tetsuya SHIBAYAMA ,  Katsushige MATSUBARA ,  Ren IMAOKA ,  Seiji MOCHIZUKI

IPC: H04N19/117 ,  H04N19/124 ,  H04N19/18 ,  H04N19/86

CPC classification number: H04N19/117 ,  H04N19/124 ,  H04N19/159 ,  H04N19/164 ,  H04N19/172 ,  H04N19/174 ,  H04N19/18 ,  H04N19/44 ,  H04N19/45 ,  H04N19/86

Abstract: To improve an image recognition rate by quickly changing a parameter in a proper manner without being affected by a transmission delay of an image encoding stream in an image receiving device that recognizes a decoded image obtained by decoding the received image encoding stream. The image receiving device includes a data receiving unit, a parameter changing unit, a decoding unit, and an image recognition unit. The data receiving unit receives an image encoding stream including image encoding data and the parameter. The parameter changing unit changes the parameter received by the data receiving unit, that is, the parameter specified for encoding performed by a sender, to a value suitable for image recognition performed in the subsequent stage. The decoding unit generates the image decoding data by decoding the received image encoding data according to the changed parameter. The image recognition unit performs image recognition on the image decoding data.

Abstract translation: 通过以适当的方式快速改变参数来提高图像识别率，而不受图像接收装置中的图像编码流的传输延迟的影响，图像接收装置识别通过解码接收到的图像编码流而获得的解码图像。 图像接收装置包括数据接收单元，参数改变单元，解码单元和图像识别单元。 数据接收单元接收包括图像编码数据和参数的图像编码流。 参数改变单元将由数据接收单元接收的参数，即由发送者执行的编码所指定的参数改变为适合在后续阶段执行的图像识别的值。 解码单元通过根据改变的参数对接收的图像编码数据进行解码来生成图像解码数据。 图像识别单元对图像解码数据执行图像识别。

公开(公告)号：US20220057950A1

公开(公告)日：2022-02-24

申请号：US17517929

申请日：2021-11-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsushige MATSUBARA ,  Seiji MOCHIZUKI

IPC: G06F3/06

Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.

公开(公告)号：US20190095324A1

公开(公告)日：2019-03-28

申请号：US16057713

申请日：2018-08-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keisuke MATSUMOTO ,  Seiji MOCHIZUKI ,  Hiroshi UEDA ,  Katsushige MATSUBARA

IPC: G06F12/06 ,  G06F7/575

Abstract: Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.

公开(公告)号：US20180367806A1

公开(公告)日：2018-12-20

申请号：US15950609

申请日：2018-04-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Seiji MOCHIZUKI ,  Katsushige MATSUBARA

IPC: H04N19/186 ,  H04N19/50 ,  H04N19/182 ,  H04N19/103 ,  H04N19/184

Abstract: A video encoding circuit includes a prediction image generation unit configured to receive a plurality of pictures, each of the pictures containing a plurality of components, search for a reference image from components of a picture itself or an already-encoded picture stored in a reference memory, and generate a prediction image based on information on a pixel contained in the reference image, the plurality of components corresponding to respective color components contained in the input picture and having wavelengths different from each other, the reference image being used for encoding of each of the plurality of components contained in the input picture, and an encoding unit configured to generate a bit stream based on the prediction image output from the prediction image generation unit, in which the prediction image generation unit outputs a reference component index indicating information on a component containing the reference image.

公开(公告)号：US20180253127A1

公开(公告)日：2018-09-06

申请号：US15858361

申请日：2017-12-29

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi UEDA ,  Ryoji HASHIMOTO ,  Taku MAEKAWA ,  Katsushige MATSUBARA ,  Keisuke MATSUMOTO

IPC: G06F1/24 ,  G06T1/20 ,  G06T1/60

Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.

公开(公告)号：US20170185521A1

公开(公告)日：2017-06-29

申请号：US15358133

申请日：2016-11-22

Applicant: Renesas Electronics Corporation

Inventor： Katsushige MATSUBARA ,  Keisuke MATSUMOTO ,  Seiji MOCHIZUKI

IPC: G06F12/0875 ,  G06F3/06

CPC classification number: G06F12/0875 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/466 ,  G06F2212/60

Abstract: Bus/memory bandwidth consumption caused by reading of auxiliary information not included in compressed data is reduced. A memory stores compressed data and auxiliary information used to read the compressed data. A semiconductor device includes a cache in which auxiliary information stored in the memory is stored, a control unit which, when a read request for reading compressed data stored in the memory is received, reads from the cache auxiliary information about the compressed data, if stored in the cache, or reads the auxiliary information about the compressed data, if not stored in the cache, from the memory and stores the auxiliary information about the compressed data in the cache, and which reads the compressed data from the memory using the auxiliary information about the compressed data, and an expansion unit to expand the compressed data read from the memory.

公开(公告)号：US20160283430A1

公开(公告)日：2016-09-29

申请号：US14965612

申请日：2015-12-10

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi UEDA ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Kenichi IWATA ,  Katsushige MATSUBARA

IPC: G06F13/40 ,  G06F13/28

CPC classification number: G06F13/4068 ,  G06F9/5066 ,  G06F13/28 ,  H04N19/176 ,  H04N19/423 ,  H04N19/436

Abstract: A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).

Abstract translation: 提供在处理单元之间传送数据的多个传送模块（402-0至402-M），以分别对应于多个处理单元（401-0至401-M）。 对于每个处理单元（401-0至401-M），第一环形总线（403-0至403-M）连接相应处理单元内的子单元和对应于处理单元的传送模块，从而形成 环形。 多个传送模块（402-0至402-M）被连接成使得它们通过第二环形总线（404）形成环形。

公开(公告)号：US20150245045A1

公开(公告)日：2015-08-27

申请号：US14620081

申请日：2015-02-11

Applicant: Renesas Electronics Corporation

Inventor： Katsushige MATSUBARA ,  Takayuki MATSUMI ,  Seiji MOCHIZUKI ,  Kenichi IWATA ,  Toshiyuki KAYA

IPC: H04N19/436 ,  H04N19/91 ,  G06T1/20

CPC classification number: H04N19/436 ,  G06T1/20 ,  H04N19/91

Abstract: The present invention provides an image processing apparatus capable of efficiently scheduling tasks and a control method for the same. An image processing apparatus according to an embodiment includes: a request receiving unit that receives requests from a plurality of pieces of content; a variable-length code processing unit which decodes or encodes the content; a plurality of image signal processing units executing tasks according to the requests in parallel; an estimating unit that estimates estimate time by which a process of the task is completed in each of the image signal processing units on the basis of a parameter of decoding or encoding used in the variable-length code processing unit; and a scheduling unit that schedules tasks executed by the plurality of image signal processing units on the basis of estimation time estimated by the estimating unit.

Abstract translation: 本发明提供能够有效地调度任务的图像处理装置及其控制方法。 根据实施例的图像处理装置包括：请求接收单元，其从多个内容接收请求; 可变长度码处理单元，其对内容进行解码或编码; 多个图像信号处理单元，根据请求并行执行任务; 估计单元，其基于在所述可变长度代码处理单元中使用的解码或编码的参数来估计每个所述图像信号处理单元中完成所述任务的处理的估计时间; 以及调度单元，其基于由所述估计单元估计的估计时间来调度由所述多个图像信号处理单元执行的任务。