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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240419605A1

    公开(公告)日：2024-12-19

    申请号：US18646506

    申请日：2024-04-25

    Applicant: Renesas Electronics Corporation

    Inventor： Ryuichi IGARASHI ,  Katsushige MATSUBARA ,  Kazuaki TERASHIMA

    IPC: G06F12/1045 ,  G06F7/544 ,  G06F12/06

    Abstract: A semiconductor device includes a scratchpad memory, a memory controller, and a MAC (multiply-accumulation) unit. The scratchpad memory is configured to store image data of N channels and includes M memories which are individually accessible, wherein M is integer of at least 2 and N is an integer of at least 2. The memory controller controls access to the scratchpad memory such that pixel data of the N channels which are arranged at a same position in image data of the N channels are respectively stored in difference memories in the M memories. The MAC unit includes a plurality of calculators to calculate pixel data of the N channels read from the scratchpad memory by using the memory controller and a weight parameter.

    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    2.
    发明申请
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 审中-公开

    公开(公告)号：US20200228842A1

    公开(公告)日：2020-07-16

    申请号：US16834616

    申请日：2020-03-30

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Katsushige MATSUBARA ,  Seiji MOCHIZUKI ,  Keisuke MATSUMOTO

    IPC: H04N19/65 ,  H04L1/00 ,  H04N19/503 ,  H04N19/159 ,  H04N19/176 ,  H04N19/42 ,  H03M7/30 ,  H03M13/00

    Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.

    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    6.
    发明申请
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 审中-公开

    公开(公告)号：US20190132611A1

    公开(公告)日：2019-05-02

    申请号：US16126739

    申请日：2018-09-10

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Katsushige MATSUBARA ,  Seiji MOCHIZUKI ,  Keisuke MATSUMOTO

    IPC: H04N19/65 ,  H04N19/42 ,  H04N19/159 ,  H04N19/176 ,  H03M13/00 ,  H03M7/30

    Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.

    SEMICONDUCTOR DEVICE, DATA PROCESSING SYSTEM, AND SEMICONDUCTOR DEVICE CONTROL METHOD
    7.
    发明申请
    SEMICONDUCTOR DEVICE, DATA PROCESSING SYSTEM, AND SEMICONDUCTOR DEVICE CONTROL METHOD 审中-公开

    公开(公告)号：US20190095338A1

    公开(公告)日：2019-03-28

    申请号：US16204222

    申请日：2018-11-29

    Applicant: Renesas Electronics Corporation

    Inventor： Katsushige MATSUBARA ,  Keisuke MATSUMOTO ,  Seiji MOCHIZUKI

    IPC: G06F12/0875 ,  G06F12/0862 ,  G06F3/06 ,  G06F12/02

    Abstract: Bus/memory bandwidth consumption caused by reading of auxiliary information not included in compressed data is reduced. A memory stores compressed data and auxiliary information used to read the compressed data. A semiconductor device includes a cache in which auxiliary information stored in the memory is stored, a control unit which, when a read request for reading compressed data stored in the memory is received, reads from the cache auxiliary information about the compressed data, if stored in the cache, or reads the auxiliary information about the compressed data, if not stored in the cache, from the memory and stores the auxiliary information about the compressed data in the cache, and which reads the compressed data from the memory using the auxiliary information about the compressed data, and an expansion unit to expand the compressed data read from the memory.

    IMAGE PROCESSING APPARATUS AND CONTROL METHOD FOR THE SAME
    8.
    发明申请
    IMAGE PROCESSING APPARATUS AND CONTROL METHOD FOR THE SAME 审中-公开

    公开(公告)号：US20170257637A1

    公开(公告)日：2017-09-07

    申请号：US15604356

    申请日：2017-05-24

    Applicant: Renesas Electronics Corporation

    Inventor： Katsushige MATSUBARA ,  Takayuki MATSUMI ,  Seiji MOCHIZUKI ,  Kenichi IWATA ,  Toshiyuki KAYA

    IPC: H04N19/436 ,  H04N19/91 ,  G06T1/20

    CPC classification number: H04N19/436 ,  G06T1/20 ,  H04N19/91

    Abstract: An in-vehicle system includes a camera having an encoder encoding video obtained by the camera, an image processing apparatus which receives the encoded video from the camera, and an image recognition processing circuit performing image recognition on decoded video data from the image processing apparatus. The image processing apparatus includes a codec processing circuit which decodes the encoded video, a plurality of image processing circuits which execute tasks in parallel, an estimating circuit which estimates estimation time in which a process of the task is completed in each of the image processing circuit on the basis of the number of access times to a bus which is obtained on the basis of a parameter of decoding used in the codec processing circuit, and a scheduling circuit which schedules tasks to be executed by the plurality of image processing circuit on the basis of the estimation time.

    VIRTUALIZATION SYSTEM AND OPERATION MANAGEMENT METHOD
    10.
    发明申请
    VIRTUALIZATION SYSTEM AND OPERATION MANAGEMENT METHOD 有权

    公开(公告)号：US20210132978A1

    公开(公告)日：2021-05-06

    申请号：US17064341

    申请日：2020-10-06

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Tetsuya SHIBAYAMA ,  Nhat Van HUYNH ,  Katsushige MATSUBARA ,  Seiji MOCHIZUKI

    IPC: G06F9/455 ,  G06F9/50

    Abstract: In a virtualization system that includes a hypervisor that performs OSID management for linking a plurality of OSs with resources, a guest OS that receives an initial value from the hypervisor and sets a OSID for each resource, and a OSID manager that sets a OSID for each resource, a new OSID created by OSID generator in OSID manager after a certain period of time has elapsed after setting the initial value is set to the guest OS and the IP (resource), and is requested to be updated to a new OSID set by the update controller in OSID manager. This enables simultaneous updating of OSID of the guest operating system and the resources, thus achieving high robustness.

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