公开(公告)号：US20110280060A1

公开(公告)日：2011-11-17

申请号：US13191232

申请日：2011-07-26

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C7/10 ,  G11C11/00

CPC classification number: G11C7/1096 ,  G11C5/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/10 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/71 ,  G11C2216/14

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract translation: 本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。 在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。 例如，集成电路可以包括设置在多层存储器中的存储单元。 在一个实施例中，存储器单元可以是第三维存储器单元。 集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。 在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。 每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。