公开(公告)号：US20120147678A1

公开(公告)日：2012-06-14

申请号：US13401661

申请日：2012-02-21

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G06F13/1668 ,  G11C5/025 ,  G11C7/1012 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1096 ,  G11C2207/2218

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract translation: 本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。 在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。 例如，集成电路可以包括设置在多层存储器中的存储单元。 在一个实施例中，存储器单元可以是第三维存储器单元。 集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。 在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。 每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

公开(公告)号：US20120063191A1

公开(公告)日：2012-03-15

申请号：US13303009

申请日：2011-11-22

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C11/21 ,  G11C11/56 ,  G11C17/00 ,  B82Y10/00

CPC classification number: G06F12/0292 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/0683 ,  G06F2212/2022

Abstract: Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.

Abstract translation: 描述了使用非易失性第三维存储器执行数据操作，包括具有被配置为存储数据的非易失性第三维存储器阵列的存储系统，所述数据包括指示磁盘驱动器上的文件位置的地址以及被配置为 处理与磁盘驱动器相关联的访问请求，将访问请求路由到非易失性第三维存储器阵列以执行数据操作，其中来自数据操作的数据用于创建磁盘驱动器的映射。 在一些示例中，非易失性第三维存储器阵列中的地址为磁盘驱动器中的另一地址提供别名。

公开(公告)号：US20120176840A1

公开(公告)日：2012-07-12

申请号：US13425256

申请日：2012-03-20

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C16/06 ,  G11C16/04

CPC classification number: H01L45/08 ,  G06F17/5045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

Abstract: Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory bocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may include non-volatile two-terminal cross-point memory arrays. The non-volatile two-terminal cross-point memory arrays can be formed on top of a logic plane. The logic plane can be fabricated in a substrate. The non-volatile two-terminal cross-point memory arrays may be vertically stacked upon one another to form a plurality of memory planes. The memory planes can be portioned into sub-planes. One or more different memory types such as Flash, SRAM, DRAM, and ROM can be emulated by the plurality of memory planes and/or sub-planes. The non-volatile two-terminal cross-point memory arrays can include a plurality of two-terminal memory elements.

Abstract translation: 描述了集成电路中的组合存储器，包括确定对逻辑块的第一要求，确定包括用于存储器块的垂直配置的存储器块的第二要求，以及使用第一要求和第二要求编译集成电路的设计。 存储器块可以包括非易失性两端交叉点存储器阵列。 非易失性双端子交叉点存储器阵列可以形成在逻辑平面的顶部。 逻辑平面可以在衬底中制造。 非易失性双端子交叉点存储器阵列可以彼此垂直地堆叠以形成多个存储器平面。 存储器平面可以分成子平面。 可以通过多个存储器平面和/或子平面来仿真一个或多个不同的存储器类型，例如闪存，SRAM，DRAM和ROM。 非易失性两端交叉点存储器阵列可以包括多个两端存储元件。

公开(公告)号：US20120069621A1

公开(公告)日：2012-03-22

申请号：US13303006

申请日：2011-11-22

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C11/21 ,  G11C17/00

CPC classification number: G06F13/4239 ,  G06F13/1694 ,  G11C7/10 ,  G11C7/22 ,  Y02D10/14 ,  Y02D10/151

Abstract: Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another.

Abstract translation: 公开了与至少一个非易失性电阻率敏感存储器通信的接口电路。 存储器包括可以具有两个端子的多个非易失性存储器元件，其可操作以将数据存储为可以通过在存储器元件上施加读取电压来确定的多个导电率曲线，并且在不存在时保留存储的数据 的权力。 可以以交叉点阵列配置布置多个存储器元件。 接口电路与例如DRAM，SRAM和FLASH等存储器类型的系统进行电气通信，并且可操作地与非易失性电阻率敏感存储器通信以模拟这些存储器类型中的一个或多个。 接口电路可以在衬底上的逻辑平面中制造，其中至少一个非易失性电阻率敏感存储器垂直定位在逻辑平面上。 非易失性电阻率敏感存储器可以彼此垂直堆叠。

公开(公告)号：US20120212646A1

公开(公告)日：2012-08-23

申请号：US13455026

申请日：2012-04-24

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: H04N5/76

CPC classification number: H04N1/2166 ,  G11C13/00 ,  H04N2101/00 ,  H04N2201/216

Abstract: An image capture device using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, a non-volatile memory card, and FLASH memory, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the image capture device. At least one of the memory arrays may be in the form of a removable memory card.

Abstract translation: 公开了使用直接寻址和非易失性的存储器阵列的图像捕获装置。 存储器阵列可用于替代和仿真多种存储器类型，例如DRAM，SRAM，非易失性RAM，非易失性存储卡和FLASH存储器。 可以随机访问存储器阵列。 存储在存储器阵列中的数据在没有电力的情况下被保留。 在图像捕获装置中可以使用一个或多个存储器阵列。 存储器阵列中的至少一个可以是可移动存储卡的形式。

公开(公告)号：US20120210052A1

公开(公告)日：2012-08-16

申请号：US13454996

申请日：2012-04-24

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G06F12/00

CPC classification number: H03M7/30 ,  G11C5/02

Abstract: An integrated circuit and method for modifying data by compressing the data in third dimensional memory technology is disclosed. In a specific embodiment, an integrated circuit is configured to perform compression of data disposed in third dimensional memory. For example, the integrated circuit can include a third dimensional memory array configured to store an input independent of storing a compressed copy of the input, a processor configured to compress the input to form the compressed copy of the input, and a controller configured to control access between the processor and the third dimensional memory array. The third dimension memory array can include one or more layers of non-volatile re-writeable two-terminal cross-point memory arrays fabricated back-end-of-the-line (BEOL) over a logic layer fabricated front-end-of-the-line (FEOL). The logic layer includes active circuitry for data operations (e.g., read and write operations) and data compression operations on the third dimension memory array.

Abstract translation: 公开了一种用于通过压缩第三维存储器技术中的数据来修改数据的集成电路和方法。 在具体实施例中，集成电路被配置为对设置在第三维存储器中的数据执行压缩。 例如，集成电路可以包括被配置为存储独立于存储输入的压缩副本的输入的第三维存储器阵列，被配置为压缩输入以形成输入的压缩副本的处理器，以及被配置为控制 处理器和第三维存储器阵列之间的访问。 第三维存储器阵列可以包括在制造的前端的逻辑层上制造后端（BEOL）的一层或多层非易失性可重写的两端交叉点存储器阵列， （FEOL）。 逻辑层包括用于第三维存储器阵列上的数据操作（例如，读和写操作）和数据压缩操作的活动电路。

公开(公告)号：US20120179862A1

公开(公告)日：2012-07-12

申请号：US13425260

申请日：2012-03-20

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G11C5/02 ,  G11C13/0002 ,  G11C2213/71 ,  Y02D10/13

Abstract: Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data.

Abstract translation: 描述访问非易失性存储器阵列，包括接收与第一数据相关联的第一数据和存储器地址，将第一数据写入第一数据的存储器地址处的非易失性存储器阵列，而不擦除存储的第二数据 在非易失性存储器阵列中的第一个数据的存储器地址写入第一个数据之前。

公开(公告)号：US20120069665A1

公开(公告)日：2012-03-22

申请号：US13303016

申请日：2011-11-22

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G06F12/0246 ,  G11C5/02 ,  G11C13/0002 ,  G11C16/102 ,  G11C16/16 ,  G11C2213/71 ,  Y02D10/13

Abstract: A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example.

Abstract translation: 公开了一种用于仿真NAND存储器系统的系统和方法。 在该方法中，接收与NAND存储器相关联的命令。 收到命令后，将根据该命令访问垂直配置的非易失性存储器阵列。 在系统中，垂直配置的非易失性存储器阵列与输入/输出控制器和存储器控制器连接。 存储器控制器也与输入/输出控制器连接。 存储器控制器可操作以与与NAND存储器相关联的命令并基于该命令来访问垂直配置的非易失性存储器阵列用于诸如读取操作或写入操作之类的数据操作。 在写入操作之前，不需要对垂直配置的非易失性存储器阵列进行擦除操作。 例如，垂直配置的非易失性存储器阵列可以被划分为平面，块和子平面。

公开(公告)号：US20120023288A1

公开(公告)日：2012-01-26

申请号：US13252937

申请日：2011-10-04

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G11C5/02 ,  G11C13/0002 ,  G11C2213/71 ,  Y02D10/13

Abstract: Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data.

Abstract translation: 描述访问非易失性存储器阵列，包括接收与第一数据相关联的第一数据和存储器地址，将第一数据写入第一数据的存储器地址处的非易失性存储器阵列，而不擦除存储的第二数据 在非易失性存储器阵列中的第一个数据的存储器地址写入第一个数据之前。

公开(公告)号：US20120210053A1

公开(公告)日：2012-08-16

申请号：US13455013

申请日：2012-04-24

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G06F12/00

CPC classification number: G11C7/24 ,  G11C5/02

Abstract: The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory.

Abstract translation: 本发明的各种实施例一般涉及半导体和存储器技术。 更具体地，本发明的各种实施例和示例涉及保护存储在一个或多个存储器装置中的数据免于未授权访问的存储器件，系统和方法。 存储器件可以包括位于包括与第三维存储器通信的有源电路的逻辑层顶部上的第三维存储器。 第三维存储器可以包括彼此垂直堆叠的多层存储器。 每个存储器层可以包括多个两端存储器元件，并且两端存储器元件可以被布置成两端交叉点阵列配置。 多层存储器中的一个或多个的至少一部分可以包括被配置为隐藏存储在多层存储器中的一个或多个层中的数据的混淆层。