利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

260 条记录 (耗时 0.034 秒)

    Patterned silicon-on-insulator layers and methods for forming the same
    21.
    发明授权
    Patterned silicon-on-insulator layers and methods for forming the same 失效
    图案化的绝缘体上硅层及其形成方法

    公开(公告)号：US07566629B2

    公开(公告)日：2009-07-28

    申请号：US11155029

    申请日：2005-06-16

    申请人： Roger Allen Booth, Jr. ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger Allen Booth, Jr. ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76243

    摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.

    摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。

    Storage Elements with Disguised Configurations and Methods of Using the Same
    23.
    发明申请
    Storage Elements with Disguised Configurations and Methods of Using the Same 审中-公开
    具有伪装配置的存储元件及其使用方法

    公开(公告)号：US20080067600A1

    公开(公告)日：2008-03-20

    申请号：US11533191

    申请日：2006-09-19

    申请人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    发明人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： H01L23/62

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是具有（1）具有源极/漏极扩散区域的金属氧化物半导体场效应晶体管（MOSFET）的集成电路（IC）的元件; （2）耦合到所述MOSFET的电熔丝（eFuse），使得所述eFuse的一部分用作所述MOSFET的栅极区域; 和（3）耦合到MOSFET的源极/漏极扩散区域的注入区域，使得源极/漏极扩散区域之间的路径用作短路或开路。 提供了许多其他方面。

    SOI hybrid structure with selective epitaxial growth of silicon
    25.
    发明授权
    SOI hybrid structure with selective epitaxial growth of silicon 有权

    公开(公告)号：US06555891B1

    公开(公告)日：2003-04-29

    申请号：US09690674

    申请日：2000-10-17

    申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    IPC分类号： H01L2900

    CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

    摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

    Redundant input/output driver circuit
    28.
    发明授权
    Redundant input/output driver circuit 失效
    冗余输入/输出驱动电路

    公开(公告)号：US06177809B1

    公开(公告)日：2001-01-23

    申请号：US09322470

    申请日：1999-05-28

    申请人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    发明人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    IPC分类号： H03K19094

    CPC分类号： H03K19/00384 ,  H03K19/0005

    摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.

    摘要翻译： 由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。 包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。 公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态 状态的第一个片外驱动电路。

    SOI/bulk hybrid substrate and method of forming the same
    30.
    发明授权
    SOI/bulk hybrid substrate and method of forming the same 有权
    SOI /散装混合基板及其形成方法

    公开(公告)号：US6107125A

    公开(公告)日：2000-08-22

    申请号：US187292

    申请日：1998-11-05

    申请人： Mark A. Jaso ,  Jack A. Mandelman ,  William R. Tonti ,  Matthew R. Wordeman

    发明人： Mark A. Jaso ,  Jack A. Mandelman ,  William R. Tonti ,  Matthew R. Wordeman

    IPC分类号： H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/00

    CPC分类号： H01L21/84 ,  H01L21/7624 ,  H01L27/1203

    摘要： A semiconductor device having areas that are semiconductor on insulator ("SOI") and areas that are bulk, single crystalline semiconductive areas is provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not be selectively grown, because a sacrificial polishing layer is deposited, is also provided.

    摘要翻译： 提供了具有半导体绝缘体（“SOI”）和作为本体的单晶半导体区域的区域的半导体器件，其中可以形成导电间隔物以将SOI区域电连接到地，以克服浮体效应， 可以与SOI发生。 此外，可以在导电间隔物的表面上形成绝缘间隔物，以将SOI区域与大块区域电隔离。 提供了制造这两种产品的新方法，其中由于牺牲抛光层的沉积，外延生长的单晶体区域不需要选择性地生长。