公开(公告)号：US10707885B2

公开(公告)日：2020-07-07

申请号：US16272236

申请日：2019-02-11

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Kenneth C. Dyer ,  Nhat Nguyen ,  Shankar Tangirala

IPC: H03M1/00 ,  H04L25/03 ,  H03M1/14 ,  H03M1/36

Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

公开(公告)号：US20200007363A1

公开(公告)日：2020-01-02

申请号：US16455479

申请日：2019-06-27

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Nhat Nguyen ,  Charles Walter Boecker

IPC: H04L25/49 ,  H04L25/03 ,  H04L7/033 ,  H04L7/00

Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

公开(公告)号：US20190245548A1

公开(公告)日：2019-08-08

申请号：US16272236

申请日：2019-02-11

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Kenneth C. Dyer ,  Nhat Nguyen ,  Shankar Tangirala

IPC: H03M1/00 ,  H04L25/03

Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

公开(公告)号：US20180152284A1

公开(公告)日：2018-05-31

申请号：US15799016

申请日：2017-10-31

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Nhat Nguyen ,  Yikui Jen Dong ,  Arash Zargaran-Yazd

IPC: H04L7/00 ,  H04L25/49 ,  H03K7/02 ,  H03L7/00

CPC classification number: H04L7/0087 ,  H03K7/02 ,  H03L7/00 ,  H04L7/0025 ,  H04L7/0337 ,  H04L25/4917

Abstract: A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.