公开(公告)号：US20240281154A1

公开(公告)日：2024-08-22

申请号：US18569518

申请日：2022-06-21

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Torsten PARTSCH ,  Brent Steven HAUKNESS ,  John Eric LINSTADT

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: DRAM cells need to be periodically refreshed to preserve the charge stored in them. The retention time is typically not the same for all DRAM cells but follows a distribution with multiple orders of magnitude difference between the retention time of cells with the highest charge loss and the cells with the lowest charge loss. Different refresh intervals are used for certain wordlines based on the required minimum retention time of the cells on those wordlines. The memory controller does not keep track of refresh addresses. After initialization of the DRAM devices, the memory controller issues a smaller number of refresh commands when compared to refreshing all wordlines at the same refresh interval.

公开(公告)号：US20230026876A1

公开(公告)日：2023-01-26

申请号：US17785269

申请日：2020-12-03

Applicant: Rambus Inc.

Inventor： Liji GOPALAKRISHNAN ,  Thomas VOGELSANG ,  John Eric LINSTADT

IPC: G06F3/06 ,  G11C11/406

Abstract: A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.

公开(公告)号：US20230008889A1

公开(公告)日：2023-01-12

申请号：US17852169

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Mark D. KELLAM

IPC: G11C11/42 ,  G02B6/12

Abstract: Multidrop optical connections are used for an optical memory module. Multiple buffer integrated circuits on a module each receive information from the host system using different wavelengths of light transmitted on the same waveguide. Multiple buffer integrated circuits each transmit information back to the CPU using different wavelengths of light transmitted on another waveguide. Wavelength resonant ring couplers disposed on the buffer integrated circuits are used to separate the wavelength being received by a particular buffer integrated circuit from the wavelengths of light destined for other buffer integrated circuits on the same waveguide. Wavelength resonant ring modulators also disposed on the buffer integrated circuits modulate specific wavelengths of light unique to each buffer integrated circuit to transmit information to the CPU.

公开(公告)号：US20220269436A1

公开(公告)日：2022-08-25

申请号：US17627478

申请日：2020-07-06

Applicant: Rambus Inc.

Inventor： Mark D. KELLAM ,  Steven C. WOO ,  Thomas VOGELSANG ,  John Eric LINSTADT

IPC: G06F3/06

Abstract: An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The set of one or more logic layers include a coupled chain of processing elements. The processing elements in the coupled chain may independently compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the coupled chain of processing elements. The processing elements in the chains may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These interfaces may access DRAM memory banks via TSVs that are not used for global I/O. These interfaces allow the processing elements to have more direct access to the data in the DRAM.

公开(公告)号：US20220083224A1

公开(公告)日：2022-03-17

申请号：US17461105

申请日：2021-08-30

Applicant: Rambus Inc.

Inventor： Michael Raymond MILLER ,  Steven C. WOO ,  Thomas VOGELSANG

IPC: G06F3/06 ,  G06F1/08

Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.

公开(公告)号：US20220013161A1

公开(公告)日：2022-01-13

申请号：US17390370

申请日：2021-07-30

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  John Eric LINSTADT ,  Liji GOPALAKRISHNAN

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G06F13/42

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.