公开(公告)号：US20090256674A1

公开(公告)日：2009-10-15

申请号：US12490545

申请日：2009-06-24

Applicant: Thomas Youbok Lee ,  James B. Nolan ,  Steve Vernier ,  Randy Yach ,  Alan Lamphier

Inventor： Thomas Youbok Lee ,  James B. Nolan ,  Steve Vernier ,  Randy Yach ,  Alan Lamphier

IPC: G05B19/00

CPC classification number: H04B1/1615 ,  B60R25/24 ,  G06K19/07 ,  G07C9/00309 ,  G07C2009/00333 ,  G07C2009/00373 ,  G07C2009/00769 ,  H04W52/0225 ,  Y02D70/166 ,  Y02D70/40

Abstract: A remote keyless entry (RKE) transponder has a programmable selective wake-up filter for determining whether the RKE transponder should wake-up to process a received signal. The wake-up filter correlates the timing of an input signal's carrier amplitude on and off time periods to a predefined programmable time period profile for a desired signal which has a certain carrier on time (time period on) and a certain carrier off time (time period off) arranged into a coded “header.” When a received signal matches the predefined time period profile, then the RKE transponder will wake-up to process the incoming signal data. The predefined time period profile may be programmable and may be stored in a header configuration register. Each RKE transponder has unique predefined time period on and time period off profiles.

Abstract translation: 远程无钥匙进入（RKE）转发器具有可编程选择性唤醒滤波器，用于确定RKE应答器是否应该被唤醒以处理接收到的信号。 唤醒滤波器将输入信号的载波幅度开和关时间周期的定时与预定的可编程时间段分布相关联，用于对于具有一定载波的时间（时间周期）和某个载波关闭时间（时间周期）的期望信号 期间关闭）排列成编码“标题”。 当接收到的信号与预定义的时间段曲线匹配时，则RKE应答器将被唤醒以处理输入的信号数据。 预定义的时间段简档可以是可编程的，并且可以存储在头部配置寄存器中。 每个RKE转发器具有独特的预定义时间段和时间段关闭配置文件。

公开(公告)号：US20090128969A1

公开(公告)日：2009-05-21

申请号：US12174802

申请日：2008-07-17

Applicant: Philippe Deval ,  Patrick Besseux ,  Randy Yach

Inventor： Philippe Deval ,  Patrick Besseux ,  Randy Yach

IPC: H02H9/04

CPC classification number: H01L27/0266 ,  H02H9/046

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capa citive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Abstract translation: 器件接口的自适应静电放电（ESD）保护在处理或安装到系统或从系统中移除时具有非常好的ESD鲁棒性。 并且当其在系统中可操作时，具有对DPI，电磁干扰（EMI）等的强大的抗扰性。 在外部连接上没有（或低电平）DPI时，ESD保护金属氧化物半导体（MOS）器件的漏极和栅极之间存在显着的电容耦合，以增强ESD保护和较低的反冲电压。 。 因此当在外部连接上检测到显着的DPI / EMI信号时，MOS ESD保护器件的漏极和栅极之间的电容耦合被断开，旁路或衰减，从而增强了器件的DPI / EMI抗扰度。

公开(公告)号：US20080315195A1

公开(公告)日：2008-12-25

申请号：US12128403

申请日：2008-05-28

Applicant: Randy Yach ,  Tommy Stevens

Inventor： Randy Yach ,  Tommy Stevens

IPC: H01L23/58 ,  H01L21/66

CPC classification number: G01R31/31717 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318511 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.

Abstract translation: 用于监测半导体制造工艺的方法产生半导体芯片晶片。 每个芯片都有一个或多个二极管。 每个二极管可寻址作为阵列的一部分，对应于芯片的物理位置，并且串联连接到堆叠。 堆叠由一个更多的垂直互连和金属触点组成。 寻址二极管和相关联的垂直互连堆栈，并测量通过阵列中的每个垂直互连堆叠的电流。

公开(公告)号：US20060017109A1

公开(公告)日：2006-01-26

申请号：US11201373

申请日：2005-08-10

Applicant: Randy Yach ,  Greg Dix

Inventor： Randy Yach ,  Greg Dix

IPC: H01L23/62

CPC classification number: H01L27/0259

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

Abstract translation: 高压ESD保护结构用于通过在可能导致破坏性击穿的电压下进行受控击穿电压来保护连接到集成电路接合焊盘的输入或输出的精细晶体管电路免受破坏性高电压ESD事件的影响 的输入和/或输出电路。 ESD保护结构能够吸收来自这些ESD事件的高电流，而不会产生危及集成电路的较高电压输入和/或输出的操作的快速恢复。 当ESD事件发生在高于ESD保护结构中电子器件（例如二极管）的受控击穿电压的电压时，ESD保护结构将导通。 来自具有高于电子器件受控击穿电压的电压的ESD事件的电流的导通可以通过可由该器件控制（触发）的ESD保护结构中的另一电子器件，例如具有高电流传导能力的晶体管 （例如，二极管）确定受控击穿电压（ESD电压被钳位到期望值）。 高压ESD保护结构可以基本上位于接合焊盘下方，并且还可以包括在接合焊盘和ESD钳位电路之间的低电容正向二极管结构。

公开(公告)号：US20050212052A1

公开(公告)日：2005-09-29

申请号：US10809659

申请日：2004-03-25

Applicant: Randy Yach ,  Greg Dix

Inventor： Randy Yach ,  Greg Dix

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L27/0259

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

Abstract translation: 高压ESD保护结构用于通过在可能导致破坏性击穿的电压下进行受控击穿电压来保护连接到集成电路接合焊盘的输入或输出的精细晶体管电路免受破坏性高电压ESD事件的影响 的输入和/或输出电路。 ESD保护结构能够吸收来自这些ESD事件的高电流，而不会产生危及集成电路的较高电压输入和/或输出的操作的快速恢复。 当ESD事件发生在高于ESD保护结构中电子器件（例如二极管）的受控击穿电压的电压时，ESD保护结构将导通。 来自具有高于电子器件受控击穿电压的电压的ESD事件的电流的导通可以通过可由该器件控制（触发）的ESD保护结构中的另一电子器件，例如具有高电流传导能力的晶体管 （例如，二极管）确定受控击穿电压（ESD电压被钳位到期望值）。 高压ESD保护结构可以基本上位于接合焊盘下方，并且还可以包括在接合焊盘和ESD钳位电路之间的低电容正向二极管结构。

公开(公告)号：US06944739B2

公开(公告)日：2005-09-13

申请号：US09957283

申请日：2001-09-20

Applicant: James R. Bartling ,  Joseph A. Thomsen ,  Randy Yach

Inventor： James R. Bartling ,  Joseph A. Thomsen ,  Randy Yach

IPC: G11C8/12 ,  G06F12/00

CPC classification number: G11C8/12

Abstract: A filter register bank, for example, for a CAN module provides parallel and serial access. The filter bank comprises a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and coupled with a first plurality of bus lines and for serial access all memory cells within a column are selectable and coupled with a second plurality of bus lines.

Abstract translation: 例如，用于CAN模块的滤波器寄存器组提供并行和串行访问。 滤波器组包括以列和行的矩阵排列的多个存储单元，其中为了并行访问，行内的所有存储单元可选择并与第一多个总线相耦合，并且用于串行访问列内的所有存储单元 可选择并且与第二多个总线线路耦合。