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21.发明申请System and Method for Providing a High-Speed Message Passing Interface for Barrier Operations in a Multi-Tiered Full-Graph Interconnect Architecture 有权在多层全图互连架构中提供用于屏障操作的高速消息传递接口的系统和方法公开(公告)号：US20090063880A1
公开(公告)日：2009-03-05
申请号：US11845225
申请日：2007-08-27
CPC分类号： G06F9/5088
摘要： A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.
摘要翻译： 提供了执行消息传递接口（MPI）作业的方法，计算机程序产品和系统。 第一处理器芯片从数据处理系统中执行MPI作业的任务的一组处理器芯片接收一组到达信号。 到达信号确定处理器芯片何时执行用于同步MPI作业任务的同步操作。 响应于从该组处理器芯片接收到一组到达信号，第一处理器芯片标识出到达信号到达第一个处理器芯片集合中最快的处理器芯片。 基于最快处理器芯片的识别，修改最快处理器芯片的操作。 该组处理器芯片包括位于数据处理系统的相同处理器簿或不同处理器簿之一中的处理器芯片。
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22.发明申请公开(公告)号：US20090063816A1
公开(公告)日：2009-03-05
申请号：US11845224
申请日：2007-08-27
CPC分类号： G06F15/17381
摘要： A method, computer program product, and system are provided for performing collective operations. In software executing on a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In software executing on the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译： 提供了一种执行集体操作的方法，计算机程序产品和系统。 在第一处理器书中在母处理器上执行的软件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包含该父 处理器和其他处理器。 在在母处理器上执行的软件中，多个处理器在逻辑上被布置为分层结构中的多个节点。 基于层次结构将集体操作发送到多个处理器。 在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。
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23.发明授权Method for data processing using a multi-tiered full-graph interconnect architecture 失效使用多层全图互连架构进行数据处理的方法公开(公告)号：US08185896B2
公开(公告)日：2012-05-22
申请号：US11845207
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/5061 , G06F2209/5012
摘要： A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
摘要翻译： 提供了一种实现多层全图互连架构的方法。 为了实现多层全图互连架构，多个处理器彼此耦合以创建多个处理器书籍。 多个处理器书联接在一起以创建多个超节点。 然后，将多个超节点耦合在一起以创建多层全图互连体系结构。 然后，数据在多层全图互连体系结构中从一个处理器传输到另一个处理器，这是基于一个寻址方案，该寻址方案至少指定了一个与要发送数据的目标处理器相关联的超级节点和一个处理器。
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24.发明授权System for data processing using a multi-tiered full-graph interconnect architecture 失效使用多层全图互连架构进行数据处理的系统公开(公告)号：US08140731B2
公开(公告)日：2012-03-20
申请号：US11845206
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
IPC分类号： G06F13/14
CPC分类号： G06F15/16
摘要： A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
摘要翻译： 提供了一种用于实现多层全图互连架构的系统。 为了实现多层全图互连架构，多个处理器彼此耦合以创建多个处理器书籍。 多个处理器书联接在一起以创建多个超节点。 然后，将多个超节点耦合在一起以创建多层全图互连体系结构。 然后，数据在多层全图互连体系结构中从一个处理器传输到另一个处理器，这是基于一个寻址方案，该寻址方案至少指定了一个与要发送数据的目标处理器相关联的超级节点和一个处理器。
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25.发明授权Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture 失效分组聚合在多层全图互连架构中的数据处理系统的虚拟通道中公开(公告)号：US08108545B2
公开(公告)日：2012-01-31
申请号：US11845227
申请日：2007-08-27
IPC分类号： G06F15/16 , G06F15/173 , H04L12/43 , H04L1/18
摘要： A mechanism is provided for packet coalescing in virtual channels of a data processing system. A first processor bundles original data into a data packet to be transmitted to a destination processor, the original data comprising payload data and overhead data. The first processor transmits the data packet to a second processor along a path to the destination processor. The second processor determines if the second processor has additional payload data destined for the same destination processor. Responsive to the second processor having the additional payload data, the second processor unbundles the data packet, adds the additional payload data to the payload data, and rebundles the payload data along with the additional payload data and the overhead data into a rebundled data packet. Then the second processor transmits the rebundled data packet to at least one other processor along the path to the destination processor.
摘要翻译： 提供了一种用于数据处理系统的虚拟通道中的分组聚合的机制。 第一处理器将原始数据捆绑到要发送到目的处理器的数据分组中，原始数据包括有效载荷数据和开销数据。 第一处理器沿着到目的地处理器的路径向第二处理器发送数据分组。 第二处理器确定第二处理器是否具有去往相同目的地处理器的附加有效载荷数据。 响应于具有附加有效载荷数据的第二处理器，第二处理器解除数据分组的捆绑，将附加的有效载荷数据添加到有效载荷数据，并将有效载荷数据连同额外的有效载荷数据和开销数据重新分组成重新绑定的数据分组。 然后，第二处理器将重新发送的数据分组传送到至少一个其他处理器，沿着到达目的地处理器的路径。
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26.发明授权System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture 有权在多层全图互连体系结构中动态支持间接路由的系统和方法公开(公告)号：US07840703B2
公开(公告)日：2010-11-23
申请号：US11845213
申请日：2007-08-27
IPC分类号： G06F15/16
CPC分类号： G06F15/17381 , H04L45/00 , H04L45/02 , H04L45/122 , H04L45/125 , H04L67/327
摘要： A method, computer program product, and system are provided for dynamically routing data through the data processing system. Data is received at a first processor that is to be transmitted to a destination processor. The data that is received includes address information. A lookup is performed in routing table data structures based on the address information to identify candidate paths through which the data is routed to the destination processor. A determination is made as to whether any of the candidate paths are not able to be used to route the data to the destination processor based on a setting of at least one identifier. A path is selected from the identified candidate paths for routing of the data based on a setting of the at least one identifier. Then, the data is transmitted from the first processor along the selected path toward the destination processor.
摘要翻译： 提供了一种通过数据处理系统动态路由数据的方法，计算机程序产品和系统。 在要发送到目的处理器的第一处理器处接收数据。 接收的数据包括地址信息。 基于地址信息在路由表数据结构中执行查找，以识别数据被路由到目的地处理器的候选路径。 基于至少一个标识符的设置，确定是否有任何候选路径不能用于将数据路由到目的地处理器。 基于所述至少一个标识符的设置，从所识别的候选路径中选择路径以路由数据。 然后，数据从所选择的路径从第一处理器发送到目的处理器。
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27.发明授权System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture 有权用于在多层全图互连架构中提供用于屏障操作的高速消息传递接口的系统和方法公开(公告)号：US07809970B2
公开(公告)日：2010-10-05
申请号：US11845225
申请日：2007-08-27
CPC分类号： G06F9/5088
摘要： A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.
摘要翻译： 提供了一种执行消息传递接口（MPI）作业的方法，计算机程序产品和系统。 第一处理器芯片从数据处理系统中执行MPI作业的任务的一组处理器芯片接收一组到达信号。 到达信号确定处理器芯片何时执行用于同步MPI作业任务的同步操作。 响应于从该组处理器芯片接收到一组到达信号，第一处理器芯片标识出到达信号到达第一个处理器芯片组中最快的处理器芯片。 基于最快处理器芯片的识别，修改最快处理器芯片的操作。 该组处理器芯片包括位于数据处理系统的相同处理器簿或不同处理器簿之一中的处理器芯片。
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28.发明申请System and Method for Packet Coalescing in Virtual Channels of a Data Processing System in a Multi-Tiered Full-Graph Interconnect Architecture 失效在多层全图互连架构中的数据处理系统的虚拟信道中的分组聚合的系统和方法公开(公告)号：US20090063817A1
公开(公告)日：2009-03-05
申请号：US11845227
申请日：2007-08-27
摘要： A method, computer program product, and system are provided for packet coalescing in virtual channels of a data processing system. A first processor bundles original data to be transmitted to a destination processor, the original data provided by a first source processor. The first processor transmits the bundle of data to a second processor along a path to the destination processor. The second processor determines if the second processor has additional data destined for the same destination processor, the additional data being provided by a second source processor that is different from the first source processor. Responsive to the second processor having additional data, the second processor unbundles the original data, adds the additional data to the original data, and rebundles the data along with the additional data. Then the second processor transmits the rebundled data to at least one other processor along the path to the destination processor.
摘要翻译： 提供了一种方法，计算机程序产品和系统，用于在数据处理系统的虚拟通道中进行分组聚合。 第一处理器将要发送到目的地处理器的原始数据捆绑，由第一源处理器提供的原始数据。 第一处理器沿着到目的地处理器的路径将数据包发送到第二处理器。 第二处理器确定第二处理器是否具有去往相同目的地处理器的附加数据，附加数据由不同于第一源处理器的第二源处理器提供。 响应于具有附加数据的第二处理器，第二处理器解除原始数据的捆绑，将附加数据添加到原始数据，并且与附加数据一起重新连接数据。 然后，第二处理器将重新发送的数据传送到至少一个其他处理器，沿着到达目的地处理器的路径。
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29.发明申请公开(公告)号：US20090063814A1
公开(公告)日：2009-03-05
申请号：US11845215
申请日：2007-08-27
CPC分类号： G06F15/17381
摘要： A method, computer program product, and system are provided for routing information through the data processing system. Data is received at a source processor within a set of processors that is to be transmitted to a destination processor, where the data includes address information. A first determination is performed as to whether the destination processor is within a same processor book as the source processor based on the address information. A second determination is performed as to whether the destination processor is within a same supernode as the source processor based on the address information if the destination processor is not within the same processor book. A routing path is identified for the data based on results of the first determination, the second determination, and one or more routing table data structures. The data is then transmitted from the source processor along the identified routing path toward the destination processor.
摘要翻译： 提供了一种通过数据处理系统路由信息的方法，计算机程序产品和系统。 在要发送到目标处理器的一组处理器内的源处理器处接收数据，其中数据包括地址信息。 基于地址信息，执行目的地处理器是否在与处理器相同的处理器簿内的第一确定。 如果目的地处理器不在相同的处理器书中，则基于地址信息来执行关于目的地处理器是否在与源处理器相同的超级节点内的第二确定。 基于第一确定，第二确定和一个或多个路由表数据结构的结果，为数据识别路由路径。 然后将数据从源处理器沿着识别的路由路径发送到目的地处理器。
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30.发明授权Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks 有权执行设置操作以在处理器执行消息传递接口任务时接收不同数量的数据公开(公告)号：US08893148B2
公开(公告)日：2014-11-18
申请号：US13524585
申请日：2012-06-15
CPC分类号： G06F9/522 , G06F9/5083
摘要： A system and method are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.
摘要翻译： 提供了一种系统和方法，用于在处理器执行消息传递接口（MPI）任务时执行用于接收不同数量的数据的建立操作。 提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 结果，可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。
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